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Technical Paper Home

Architectures

  • Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)

    Published on January 17, 2025
  • Design Space for the Device-Circuit Codesign of NVM-Based CIM Accelerators (TSMC)

    Published on January 15, 2025
  • Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)

    Published on January 15, 2025
  • AI Accelerators for Homomorphic Encryption Workloads

    Published on January 15, 2025
  • Designing Heterogeneous AI Acceleration SoCs

    Published on January 6, 2025
  • In-Depth Study of Low-Power MCUs For Wearables (EPFL)

    Published on December 28, 2024
  • Chiplet-Based NPUs to Accelerate Vehicular AI Perception Workloads

    Published on December 2, 2024
  • STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)

    Published on November 27, 2024
  • Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)

    Published on November 27, 2024
  • Pooling CPU Memory for LLM Inference With Lower Latency and Higher Throughput (UC Berkeley)

    Published on November 26, 2024
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