Technical Paper Home

Architectures

• Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)

  Published on March 18, 2026

• Analysis of the Evolving Landscape of Ultra-low-power Edge AI Processors (U. of Austria, ETH Zurich)

  Published on March 17, 2026

• Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)

  Published on March 16, 2026

• Neuromorphic Computing Platform In Perovskite Nickelates (UCSD, Rutgers)

  Published on March 11, 2026

• Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)

  Published on March 9, 2026

• A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)

  Published on March 9, 2026

• 10-Year Roadmap for AI + Hardware (UIUC, UCLA, Stanford et al.)

  Published on March 6, 2026

• Optimizing In-Memory AI Accelerators Across Multiple Workloads (KAUST, Compumacy)

  Published on March 6, 2026

• RPU: A Chiplet-Based Architecture To Address The Challenges of the Modern Memory Wall (Harvard University)

  Published on March 4, 2026

• 5 Systems-Level Attack Surfaces That Are Architectural Consequences of Edge-Local Deployment (Imperial College London)

  Published on March 2, 2026
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