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Memory

• New Spintronics Manufacturing Process, Allowing Scaling Down To Sub-5nm (U. of Minnesota/NIST)

  Published on March 20, 2023

• Solving The Reliability Problem Of Memristor-Based Artificial Neural Networks

  Published on March 19, 2023

• Shift Register-In-Memory Architecture

  Published on March 19, 2023

• Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language

  Published on March 19, 2023

• FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)

  Published on March 15, 2023

• Co-Design View of Cross-Bar Based Compute-In-Memory

  Published on March 15, 2023

• CXL-Based Memory Pooling System Meets Cloud Performance Goals And Significantly Reduces DRAM Cost

  Published on March 5, 2023

• Ternary LIM Operation of the TNAND and TNOR Universal Gates Using DG Feedback FETs

  Published on March 4, 2023

• Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM

  Published on March 4, 2023

• Review of Methods to Design Secure Memristor Computing Systems

  Published on February 27, 2023
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