Technical Paper Home

Memory

• Index-Based Multi-Core BDD Package With Dynamic Memory Management & Reduced Fragmentation

  Published on February 26, 2023

• In-Memory Computing: Assessing Multilevel RRAM-Based VMM Operations

  Published on February 26, 2023

• ISA and Microarchitecture Extensions Over Dense Matrix Engines to Support Flexible Structured Sparsity for CPUs (Georgia Tech, Intel Labs)

  Published on February 24, 2023

• HBM-Enabled FPGA-Based Graph Processing Accelerator

  Published on February 19, 2023

• Review of Tools & Techniques for DL Edge Inference

  Published on February 16, 2023

• Emulation System for Racetrack Memories Based on FPGA

  Published on February 13, 2023

• Advanced Packaging for High-Bandwidth Memory: Influences of TSV size, TSV Aspect Ratio And Annealing Temperature

  Published on February 13, 2023

• Side-Channel Attacks Via Cache On the RISC-V Processor Configuration

  Published on January 29, 2023

• Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs

  Published on January 29, 2023

• Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)

  Published on January 29, 2023
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