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Design & Verification

• HW/SW Co-Design to Configure DNN Models On Energy Harvesting Devices

  Published on July 20, 2022

• Fast and Flexible FPGA-based NoC Hybrid Emulation

  Published on July 14, 2022

• A Safety-Oriented System Hardware Architecture Exploration Framework

  Published on July 12, 2022

• Heterogeneous Redundant Circuit Design Approaches for FPGAs

  Published on July 12, 2022

• MIT & UC Berkeley: “Exo” Programming Language Writes High Performance Code For HW Accelerators

  Published on July 11, 2022

• TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms

  Published on July 4, 2022

• Coverage-Directed Test Selection Method for Automatic Test Biasing During Simulation-Based Verification

  Published on June 22, 2022

• Designing and Simulating Low-Voltage CMOS Circuits Using Four-Parameter Model

  Published on June 20, 2022

• Hardware Dynamic IFT Mechanism That Scales to Complex Open-Source RISC-V Processors

  Published on June 20, 2022

• U. Of Florida: Protecting Chip-Design IP From Reverse-Engineering

  Published on June 13, 2022
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