Technical Paper Home

Design & Verification

• Automotive MCUs: Digital Twin of the LBIST Functionality

  Published on February 15, 2023

• Hardware Virtualization Support in the RISC-V CVA6 Core

  Published on February 8, 2023

• Mitigating Silent Data Corruptions in High Performance Computing

  Published on January 29, 2023

• Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)

  Published on January 16, 2023

• Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies

  Published on January 11, 2023

• Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)

  Published on January 10, 2023

• FPGA-Based Prototyping Framework For Processing In DRAM (ETH Zurich & TOBB Univ.)

  Published on January 10, 2023

• Efficient Gated Clock Design Approach for LFSR

  Published on December 20, 2022

• Hardware Fuzzing (U. of Michigan, Google, Virginia Tech)

  Published on December 18, 2022

• Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)

  Published on December 15, 2022
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