Technical Paper Home

Design & Verification

• Automated Tool Flow From Domain-Specific Languages To Generate Massively Parallel Accelerators on HBM-Equipped FPGAs

  Published on April 12, 2023

• Hybrid Hardware Fuzzer, Combining Capabilities of Formal Verification Methods And Fuzzing Tools

  Published on April 11, 2023

• Digital Neuromorphic Processor: Algorithm-HW Co-design (imec / KU Leuven)

  Published on April 11, 2023

• Design Considerations and Recent Advancements in Chiplets (UC Berkeley/ Peking University)

  Published on April 10, 2023

• Scalable, Shared-L1-Memory Manycore RISC-V System

  Published on April 10, 2023

• Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures

  Published on April 9, 2023

• Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips

  Published on March 30, 2023

• Logic Locking at the RTL, Leveraging The Behavioral State Transition Coding For Obfuscation (University of Florida)

  Published on March 25, 2023

• 3D-IC: Operator Learning Framework For Ultra-Fast 3D Chip Thermal Prediction Under Multiple Chip Design Configurations

  Published on March 24, 2023

• Feasibility of Using Domain Wall-Magnetic Tunnel Junction for Magnetic Analog Addressable Memories

  Published on March 23, 2023
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