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Design & Verification

• Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant

  Published on August 7, 2023

• A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput

  Published on August 7, 2023

• A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V

  Published on August 2, 2023

• CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall

  Published on August 1, 2023

• A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership

  Published on July 20, 2023

• Analog On-Chip Learning Circuits In Mixed-Signal Neuromorphic SNNs

  Published on July 20, 2023

• System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR

  Published on July 15, 2023

• Hardware-Efficient Approach To Defend Against Fault Attacks

  Published on July 13, 2023

• An Advanced Modeling Approach For Cyclic Safety Mechanisms In A Fault Tree Analysis

  Published on July 8, 2023

• Heterogeneous Integration As A Path Towards Sustainable Computing, Using Chiplets

  Published on July 6, 2023
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