Technical Paper Home

Design & Verification

• Functional Safety Verification Of Serial Peripheral Interface

  Published on October 3, 2022

• Speeding-Up Thermal Simulations Of Chips With ML

  Published on October 2, 2022

• Six Qubit Processor (TU Delft, QuTech, TNO)

  Published on September 29, 2022

• Framework Based on an RISC-V Microprocessor Supporting LiM Operations

  Published on September 29, 2022

• Graph-Based, Formal Equivalence Checking Method

  Published on September 14, 2022

• Convolutional Neural Networks: Co-Design of Hardware Architecture and Compression Algorithm

  Published on September 7, 2022

• New Processor Fuzzing Mechanism

  Published on September 7, 2022

• Overview of Hardware-In-The-Loop (HIL) Simulations

  Published on September 2, 2022

• Artificial Neural Network (ANN)-Based Model To Evaluate The Characteristics of A Nanosheet FET (NSFET)

  Published on September 2, 2022

• Algorithm HW Framework That Minimizes Accuracy Degradation, Data Movement, And Energy Consumption Of DNN Accelerators (Georgia Tech)

  Published on August 31, 2022
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