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Design & Verification

• A Comparative Analysis of Computer-Aided Design Tools for Complex Power Electronics Systems

  Published on January 21, 2022

• AKER: A Design and Verification Framework for Safe and Secure SoC Access Control

  Published on November 12, 2021

• Dynamic in-chip current distribution simulation technology for power device layout design

  Published on November 12, 2021

• Chip Package Co-design and Physical Verification for Heterogeneous Integration

  Published on November 12, 2021

• Simulation-Based Fault Analysis for Resilient System-On-Chip Design

  Published on November 12, 2021

• Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance

  Published on November 12, 2021

• A New Multi-Stimuli-Based Simulation Method for ESD Design Verification

  Published on November 12, 2021

• HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment

  Published on November 9, 2021

• Modeling electrical conduction in resistive-switching memory through machine learning

  Published on October 4, 2021

• A Compact Model For Scalable MTJ Simulation

  Published on August 24, 2021
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