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• Logic Locking at the RTL, Leveraging The Behavioral State Transition Coding For Obfuscation (University of Florida)

  Published on March 25, 2023

• Hardware-Based Confidential Computing (NIST)

  Published on March 10, 2023

• Microarchitectural Side-Channel Attacks And Defenses On Non-Volatile RAM

  Published on March 4, 2023

• Review of Methods to Design Secure Memristor Computing Systems

  Published on February 27, 2023

• Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V

  Published on February 26, 2023

• Formal Processor Model Providing Secure Speculation For The Constant-Time Policy

  Published on February 24, 2023

• HW-SW Co-Design Solution For Building Side-Channel-Protected ML Hardware

  Published on February 19, 2023

• Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase

  Published on February 8, 2023

• RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks

  Published on February 8, 2023

• Side-Channel Attacks Via Cache On the RISC-V Processor Configuration

  Published on January 29, 2023
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