Technical Paper Home

Power & Performance

• Non-ideal Subthreshold Swing In Aligned CNTs Due To Variable Occupancy Discrete Charge Traps (Berkeley Lab, Sandia)

  Published on August 5, 2025

• LLM Inference: Core Bottlenecks Imposed By Memory, Compute Capacity, Synchronization Overheads (NVIDIA)

  Published on August 1, 2025

• Statistical BER Analysis For Two Types Of Communication Systems In Chiplet Integration (TSMC)

  Published on August 1, 2025

• 3D Heterogeneous Integration System To Accelerate LLMs (Georgia Tech)

  Published on July 30, 2025

• Preventing End-to-End Slowdowns In Accelerated Chip Multi-Processors (Cornell University, Intel Labs)

  Published on July 30, 2025

• Nanoimprint-Based Dielectric Patterning for Fine-Pitch Hybrid Bonding (Seoul National Univ. of Science and Technology)

  Published on July 30, 2025

• Implications of Scalable Neuromorphic Computing (Sandia National Laboratories)

  Published on July 30, 2025

• On-Die And In-Package Interconnects: eBook

  Published on July 28, 2025

• Computer Architecture Extending The Von Neumann Model With A Dedicated Reasoning Unit For Native Artificial General Intelligence (TU Munich, Pace U.)

  Published on July 23, 2025

• Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)

  Published on July 22, 2025
Page 17 of 73
• « First
• ‹ Previous
• 13
• 14
• 15
• 16
• 17
• 18
• 19
• 20
• 21
• Next ›
• Last »