A new technical paper titled “RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors” was published by researchers at Cornell University and Intel Labs.
Abstract
“Recent chip multiprocessors incorporate several on-chip accelerators, marking the beginning of the Accelerated Chip Multi-Processor (XMP) era in datacenters. Despite the close proximity of accelerators and general-purpose cores, offloading functions to accelerators may not always be beneficial. Offloading to hardware accelerators can introduce several end-to-end overheads that can negate the speedup of the accelerable function. In this paper, we design RACER, a hardware architecture and runtime system that evades the danger of end-to-end slowdowns when using hardware acceleration. RACER leverages a low-overhead interface between general-purpose cores and on-chip accelerators, fine-grained context switching, accelerator-initiated preemption, and seamless data motion between general-purpose cores and accelerators to improve the performance of workloads that use on-chip accelerators. We evaluate RACER on five representative request processing workloads featuring diverse memory access patterns, accelerable functions, and compute intensities. RACER improves the performance of hardware acceleration on a real XMP by an average of 1.31 × on a range of diverse workloads and guarantees that accelerator offloads never cause slowdowns.”
Find the technical paper here. July 2025.
Neel Patel, Ren Wang, and Mohammad Alian. “RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors.” ACM Trans. Archit. Code Optim. July 2025. https://doi.org/10.1145/3750448
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