tag: Intel Labs

Improving Performance and Power Efficiency By Safely Eliminating Load Instruction Execution (ETH Zürich, Intel)
By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A technical paper titled “Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution” was published by researchers at ETH Zürich and Intel Corporation.  This paper earned the Best Paper Award in the International Symposium on Computer Architecture (ISCA). Abstract: "Load instructions often limit instruction-level parallelism (ILP) in modern pr... » read more

Chip Industry Technical Paper Roundup: July 22
By Linda Christensen - 22 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=245 /] More ReadingTechnical Paper Library home » read more

NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)
By Technical Paper Link - 16 Jul, 2024 - Comments: 0

A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

Research Bits: July 8
By Liz Allan - 08 Jul, 2024 - Comments: 0

2D TFETS for neuromorphic computing Researchers from the University of California Santa Barbara and Intel Labs used 2D transition metal dichalcogenide (TMD)-based tunnel-field-effect transistors (TFETs) in a neuromorphic computing platform, bringing the energy requirements to within two orders of magnitude (about 100 times) the amount used by the human brain. The 2D TFETs have lower off-sta... » read more

Chip Industry Technical Paper Roundup: Dec 18
By Linda Christensen - 18 Dec, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=176 /] More ReadingTechnical Paper Library home » read more

A Survey Of Recent Advances In Spiking Neural Networks From Algorithms To HW Acceleration
By Technical Paper Link - 13 Dec, 2023 - Comments: 0

A technical paper titled “Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural networks: from Algorithms to Technology” was published by researchers at Intel Labs, University of California Santa Cruz, University of Wisconsin-Madison, and University of Southern California. Abstract: "Neuromorphic computing and, in particular, spiking neural networks (SNNs) have becom... » read more

Chip Industry’s Technical Paper Roundup: Apr. 4
By Linda Christensen - 04 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=90 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

CXL Memory: Detailed Characterization Analysis Using Micro-Benchmarks And Real Applications (UIUC, Intel Labs)
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices" was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. Abstract: "The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based... » read more

Chip Industry’s Technical Paper Roundup: Feb. 28
By Linda Christensen - 28 Feb, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=83 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

ISA and Microarchitecture Extensions Over Dense Matrix Engines to Support Flexible Structured Sparsity for CPUs (Georgia Tech, Intel Labs)
By Technical Paper Link - 24 Feb, 2023 - Comments: 0

A technical paper titled "VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs" was published (preprint) by researchers at Georgia Tech and Intel Labs. Abstract: "Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines accessible v... » read more

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