Chip Industry’s Technical Paper Roundup: Apr. 4

Demystifying CXL memory; physical design macro placement; 3-gated reconfigurable FETs; ALD for wafer bonding beyond silicon; self-adaptive HW with ReRAMs for neurocomputing; SiC & quantum nanophotonic HW; covert channel and PDN; scalable ALD for 2D semiconductors.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices University of Illinois Urbana-Champaign (UIUC) and Intel Labs
AutoDMP: Automated DREAMPlace-based Macro Placement NVIDIA
Large-area synthesis of high electrical performance MoS2 by a commercially scalable atomic layer deposition process University of Southampton, LMU Munich, and VTT Technical Research Centre of Finland
Insights into the Temperature Dependent Switching Behaviour of Three-Gated Reconfigurable Field Effect Transistors NaMLAB and TU Dresden
Utilizing photonic band gap in triangular silicon carbide structures for efficient quantum nanophotonic hardware UC Davis
Room-temperature bonding of Al2O3 thin films deposited using atomic layer deposition Kyushu University
A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing Infineon Technologies, Politecnico di Milano and IUNET, Weebit Nano, and CEA Leti
CPU to FPGA Power Covert Channel in FPGA-SoCs TU Munich and Fraunhofer Research Institution AISEC

If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate.

More Reading
Technical Paper Library home


Leave a Reply

(Note: This name will be displayed publicly)