Chip Industry Technical Paper Roundup: Dec. 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=497 /] Find more semiconductor research papers here. » read more

Comprehensive Performance Bound and Bottleneck Analysis Of Neuromorphic Accelerators (Harvard, Politecnico di Torino, Intel et al.)


A new technical paper titled "Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators" was published by researchers at Harvard University, Politecnico di Torino, Intel, LMU Munich, Accenture Labs, BootLoop AI, TU Delft and Wordly. Abstract "Neuromorphic accelerators offer promising platforms for machine learning (ML) inference by leveraging event-driven, spatially-expa... » read more

Chip Industry’s Technical Paper Roundup: Apr. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=90 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Large Area Process For Atomically Thin 2D Semiconductor, Using Scalable ALD


A new technical paper titled "Large-area synthesis of high electrical performance MoS2  by a commercially scalable atomic layer deposition process" by researchers at the University of Southampton, LMU Munich, and VTT Technical Research Centre of Finland. Abstract: "This work demonstrates a large area process for atomically thin 2D semiconductors to unlock the technological upscale required... » read more