Chip Industry Technical Paper Roundup: Dec 18

AI accelerator security; energy-efficient exposed datapath architecture with RISC-V; spiking neural networks advances; defect detection; side-channel analysis; clean assembly of vdW heterostructures; radar processors; vdW computing magnets.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
A Unified Hardware-based Threat Detector for AI Accelerators Nanyang Technological University and Tsinghua University
Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode Tampere University
Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural networks: from Algorithms to Technology Intel Labs, UCSC, University of Wisconsin-Madison, and USC
Improved Defect Detection and Classification Method for Advanced IC Nodes by Using Slicing Aided Hyper Inference with Refinement Strategy Ghent University, imec, and SCREEN SPE
Beyond the Last Layer: Deep Feature Loss Functions in Side-channel Analysis Nanyang Technological University, Radboud University, and TU Delft
Clean assembly of van der Waals heterostructures using silicon nitride membranes University of Manchester, Imperial College London, National Institute for Materials Science (Japan), and University of Lancaster
Ellora: Exploring Low-Power OFDM-based
Radar Processors using Approximate Computing
UC Irvine, University of Wisconsin-Madison, and TCS Research
Magnetic properties of intercalated quasi-2D Fe3-xGeTe2 van der Waals magnet UT El Paso,NIST, University of Edinburgh, Donostia International Physics Centre (DIPC), Hampton University, and Brookhaven National Laboratory

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