tag: Nanyang Technological University

Research Bits: Dec. 3
By Jesse Allen - 03 Dec, 2024 - Comments: 0

Self-assembly of mixed-metal oxide arrays Researchers from North Carolina State University and Iowa State University demonstrated a technique for self-assembling electronic devices. The proof-of-concept work was used to create diodes and transistors with high yield and could be used for more complex electronic devices. “Our self-assembling approach is significantly faster and less expensi... » read more

Research Bits: Nov. 25
By Jesse Allen - 25 Nov, 2024 - Comments: 0

3D-printed ESD protection Researchers from Lawrence Livermore National Laboratory developed a printable elastomeric silicone foam for electronics packaging that provides both mechanical and electrostatic discharge (ESD) protection. The team used a 3D printing technique called direct ink writing (DIW), an extrusion process in which a paste with controlled rheological properties such as elast... » read more

Chip Industry Technical Paper Roundup: May 28
By Linda Christensen - 28 May, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=229 /] More ReadingTechnical Paper Library home » read more

High Performance and Low-Noise Hardware Board For Side-Channel Evaluations
By Technical Paper Link - 21 May, 2024 - Comments: 0

A new technical paper titled "EFFLUX-F2: A High Performance Hardware Security Evaluation Board" was published by researchers at Nanyang Technological University (Singapore) and Indian Institute of Technology Jodhpur. Abstract "Side-channel analysis has become a cornerstone of modern hardware security evaluation for cryptographic accelerators. Recently, these techniques are also being applie... » read more

Chip Industry Week In Review
By The SE Staff - 02 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

Chip Industry Week In Review
By The SE Staff - 05 Jan, 2024 - Comments: 0

By Susan Rambo, Jesse Allen, and Liz Allan The U.S. government will provide about $162 million in federal incentives, under the CHIPS and Science Act, to help Microchip onshore its semiconductor supply chain. The move is aimed at securing a reliable domestic supply of MCUs and mature-node chips. “Today’s announcement will help propel semiconductor manufacturing projects in Colorado and O... » read more

Chip Industry Technical Paper Roundup: Dec 18
By Linda Christensen - 18 Dec, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=176 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review
By The SE Staff - 15 Dec, 2023 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

Hardware-Based Methodology To Protect AI Accelerators
By Technical Paper Link - 13 Dec, 2023 - Comments: 0

A technical paper titled “A Unified Hardware-based Threat Detector for AI Accelerators” was published by researchers at Nanyang Technological University and Tsinghua University. Abstract: "The proliferation of AI technology gives rise to a variety of security threats, which significantly compromise the confidentiality and integrity of AI models and applications. Existing software-based so... » read more

More Efficient Side-Channel Analysis By Applying Two Deep Feature Loss Functions
By Technical Paper Link - 12 Dec, 2023 - Comments: 0

A technical paper titled “Beyond the Last Layer: Deep Feature Loss Functions in Side-channel Analysis” was published by researchers at Nanyang Technological University, Radboud University, and Delft University of Technology. Abstract: "This paper provides a novel perspective on improving the efficiency of side-channel analysis by applying two deep feature loss functions: Soft Nearest Neig... » read more

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