Special Reports

Partitioning In The Chiplet Era

By: Ann Mutschler

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.
Using AI To Glue Disparate IC Ecosystem Data

By: Ed Sperling and Ann Mutschler

Why the chip industry is so focused on large language models for designing and manufacturing chips, and what problems need...
Memory Fundamentals For Engineers

By: The SE Staff

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and...

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Top Stories

Preparing For Ferroelectric Devices

Managing crystal structure for ferroelectric performance.

Barriers To Chiplet Sockets

Perfection sometimes stands in the way of progress, and there is evidence this may be h...

RAG-Enabled AI Stops Hallucinations, Adds Sources

New GenAI method enables better answers and performs more functions.

Pressure Builds To Adopt Virtual Prototypes

Creating complex multi-chiplet systems is no longer a back-of-the-envelope diagram, but...

Devising Security Solutions For Hardware Threats

Keeping up with attackers is proving to be a major challenge with no easy answers; trai...

Optimizing Wafer Edge Processes For Chip Stacking

Several critical processes address wafer flatness, wafer edge defects and what's needed...

How Die Dimensions Challenge Assembly Processes

Chiplet-based products must accommodate small differences in die size and bump pitch, p...

New Materials Are in High Demand

Development methodologies combine old and new techniques, but getting any new material ...

Managing EMI in High-Density Integration

Controlling interference in today’s SoCs and advanced packaging requires a combinatio...

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that i...

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations...

CXL Thriving As Memory Link

Adoption of Compute Express Link protocol spreads as way to connect memories.

more top stories »

Latest News

Chip Industry Week In Review

Amkor-TSMC deal; new law speeds semiconductor projects; NSTC launch; quartz supply; chiplet partitioning; semiconductor materials; ferroelectric devices; data cen...

Chip Industry Week In Review

Google's AlphaChip; 300mm fab equip spending; TSMC-EDA partnerships; $123M CHIPS Act; CXL memory standards; MIPI's A-PHY v2.0; 12-stack HBM3E; LLMs for chip desig...

more news »



Research

Research Bits: Oct. 1

Rust-resistant coating for 2D semiconductors; polymeric materi...

Chip Industry Technical Paper Roundup: Oct. 1

KAN for lightweight edge inference; bendable non-silicon RISC-...

Research Bits: Sept. 24

Novel memories: Modeling negative capacitance; nonvolatility o...

more research »



Startup Corner

Startup Funding: Q2 2024

Big rounds for AI chips; 91 startups raise $2.6 billion.

Startup Funding: March 2024

Investors connect with interconnects; $1.1 billion for 39 comp...

more startups »

Videos

Working With Chiplets


Data Routing In Heterogeneous Chip Designs


Emerging Technologies Driving Heterogeneous Integration


Real-Time Safety Monitoring


Knowledge Centers / Entities, people and technologies explored