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Packaging

• Designing a 2048-Chiplet, 14336-Core Waferscale Processor

  Published on March 14, 2022

• Warpage Of Compression Molded SiP Strips

  Published on February 17, 2022

• Topology for Substrate Routing in Semiconductor Package Design

  Published on February 15, 2022

• Impact Modifiers and Compatibilizers for Versatile Epoxy-Based Adhesive Films with Curing and Deoxidizing Capabilities

  Published on February 4, 2022

• X-ray Imaging of Silicon Die Within Fully Packaged Semiconductor Devices

  Published on January 21, 2022

• Conceptualized Improvement on Transparent Glass Die for a Robust Manufacturing Process

  Published on January 17, 2022

• TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems

  Published on December 23, 2021

• A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

  Published on December 23, 2021

• Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

  Published on December 23, 2021

• Research on the Humidity Resistance Reliability of Different Packaging Structures

  Published on December 23, 2021
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