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Die-level Thinning and Integrating Route For Singulated MPW Chips Using Both Silicon Sensors and CMOS Devices

Researchers report “Die-Level Thinning for Flip-Chip Integration on Flexible Substrates.”

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Abstract

“Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors.”

Find the “Die-Level Thinning for Flip-Chip Integration on Flexible Substrates” open access technical paper here. Published March 2022.

Malik, M.H.; Tsiamis, A.; Zangl, H.; Binder, A.; Mitra, S.; Roshanghias, A. Die-Level Thinning for Flip-Chip Integration on Flexible Substrates. Electronics 2022, 11, 849. https://doi.org/10.3390/electronics11060849

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