Low Power-High Performance

Top Stories

Managing The Huge Power Demands Of AI Everywhere

More efficient hardware, better planning, and better utilization of available power can help significantly.

New AI Data Types Emerge

Several PPA considerations mean no single type of data is ideal for all AI models.

Big Changes Ahead For Analog Design

In-house flows are unable to keep up with foundry PDKs and heterogeneous integration, but commercial EDA tools add their own set of challenges.

How Big A Deal Is Aging?

Aging must be understood, analyzed, and mastered. Until then, additional margins are the only way out.

Unbundling Analog From Digital Where It Makes Sense

The shift toward heterogeneous integration and advanced packaging have changed the dynamics of mixed-signal design — and created some new issues.

The Cost Of EDA Data Storage And Processing Efficiency

Sustainability in the EDA process is less about the environment and more about preserving resources to speed up run times.

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are u...

CXL Thriving As Memory Link

Adoption of Compute Express Link protocol spreads as way to connect memories.

Is PPA Relevant Today?

Power, performance, and area/cost have been the three optimization targets for decades, but are they pertinent for today's complex systems?

Higher Density, More Data Create New Bottlenecks In AI Chips

More options are available, but each comes with tradeoffs and adds to complexity.

More Top Stories »



Round Tables

Big Changes Ahead For Analog Design

In-house flows are unable to keep up with foundry PDKs and heterogeneous integration, but commercial EDA tools add their own set of challenges.

Unbundling Analog From Digital Where It Makes Sense

The shift toward heterogeneous integration and advanced packaging have changed the dynamics of mixed-signal design — and created some new issues.

Striking A Balance On Efficiency, Performance, And Cost

More efficient designs can save a lot of power, but in the past those savings have been co-opted for higher performance.

Where Power Savings Really Count

How chiplets and advanced packaging will affect power efficiency, and where design teams can have the biggest impact on energy consumption.

Managing kW Power Budgets

Strategies for dealing with increasing compute demands from AI and other applications.

More Roundtables »



Multimedia

Next-Gen High-Speed Communication In Data Centers

New approaches to moving more data faster and more efficiently.

Real-World Applications Of Computational Fluid Dynamics

How faster processing is revolutionizing different industries.

Making Electronics More Efficient

Challenges and future directions for disaggregating SoCs.

Challenges With Chiplets And Power Delivery

Benefits and challenges in heterogeneous integration.

New Issues In Power Semiconductors

Challenges increase with higher voltage and heterogeneous integration in advanced packages.

More Multimedia »



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Knowledge Centers
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  Trending Articles

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

Hybrid Bonding Makes Strides Toward Manufacturability

Companies are selecting preferred flows, but the process details are changing rapidly to meet the needs of different applications.

Americas Chip Funding Energizes Industry

Massive government infusions aim to improve security and supply chain robustness.

Advanced Packaging Driving New Collaboration Across Supply Chain

Rising complexity is changing the way companies engage and interact, but long-standing barriers in communication, culture, and IP protection are slowing progress.

Chiplets Make Progress Using Interconnects As Glue

Industry learning expands as more SoCs are disaggregated at leading edge, opening door to more third-party chiplets.