Low Power-High Performance

Top Stories

Development Flows For Chiplets
A chiplet economy requires standards, organization, and tools — and that's a problem.
Published on May 15th, 2025 by Brian Bailey

AI Accelerators Moving Out From Data Centers
Chiplets will be a key enabler for customizing designs at every level, from edge devices to the cloud. AI is a key driver, but it's not the only one.
Published on May 15th, 2025 by Ann Mutschler

Chiplet Tradeoffs And Limitations
Multi-die assemblies offer more flexibility, but figuring out the right amount of customization can have a big impact on power, performance, and cost.
Published on April 10th, 2025 by Ann Mutschler

Implementing AI Activation Functions
Why flexibility, area, and performance are traded off in AI inferencing designs.
Published on April 10th, 2025 by Bryon Moyer

3D-IC Ecosystem Starts To Take Form
Before any advancement can go mainstream, it requires an ecosystem. Chiplets are a first step.
Published on April 10th, 2025 by Brian Bailey

3D-IC For The Masses
Advanced assemblies have enabled an unprecedented rate of advancement in the data center, especially for neural processing, but can it expand beyon...
Published on March 13th, 2025 by Brian Bailey

Chiplets Add New Power Issues
Well-understood challenges become much more complicated when SoCs are disaggregated.
Published on March 13th, 2025 by Ann Mutschler

Integrating Data From Design, Manufacturing, And The Field
Knowing where circuits came from, and the conditions in which they operate, can help designers optimize devices already in the field.
Published on March 13th, 2025 by Adam Kovac

What Scares Chip Engineers About Generative AI
ChatGPT isn’t coming for your job, but that doesn’t mean there’s nothing to be concerned about.
Published on February 26th, 2025 by Adam Kovac

Signal Integrity Plays Increasingly Critical Role In Chip...
Chiplet design engineers have complex new considerations compared to PCB concepts.
Published on February 13th, 2025 by Ann Mutschler

More Top Stories »



Round Tables

AI Accelerators Moving Out From Data Centers
Chiplets will be a key enabler for customizing designs at every level, from edge devices to the cloud. AI is a key driver, but it's not the only one.
Published on May 15th, 2025 by Ann Mutschler

What Scares Chip Engineers About Generative AI
ChatGPT isn’t coming for your job, but that doesn’t mean there’s nothing to be concerned about.
Published on February 26th, 2025 by Adam Kovac

AI Won’t Replace Subject Matter Experts
But it could help with mundane tasks, freeing up designers to focus on more intricate problems.
Published on January 15th, 2025 by Adam Kovac

Aging, Complexity, And AI In Analog Design
Where digital and analog designs are overlapping, and why it's becoming more difficult to ensure they work as expected over their lifetimes.
Published on November 27th, 2024 by Ed Sperling

Big Changes Ahead For Analog Design
In-house flows are unable to keep up with foundry PDKs and heterogeneous integration, but commercial EDA tools add their own set of challenges.
Published on November 6th, 2024 by Ed Sperling

More Roundtables »



Multimedia

The Road To Super Chips
Challenges in achieving orders of magnitude performance improvements in processors.
Published on January 27th, 2025 by Ed Sperling

Next-Gen High-Speed Communication In Data Centers
New approaches to moving more data faster and more efficiently.
Published on August 21st, 2024 by Ed Sperling

Real-World Applications Of Computational Fluid Dynamics
How faster processing is revolutionizing different industries.
Published on August 5th, 2024 by Ed Sperling

Making Electronics More Efficient
Challenges and future directions for disaggregating SoCs.
Published on July 31st, 2024 by Ed Sperling

Challenges With Chiplets And Power Delivery
Benefits and challenges in heterogeneous integration.
Published on April 15th, 2024 by Ed Sperling

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Spotlight On Reliability

Optimizing Analog With Layout In The Loop
Improving parasitic estimation and enabling partial layout extraction earlier...
May 15, 2025
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Best Of Both: LP & HP

Best Practices For Power-Aware Verification: Because Desi...
Treating power intent as a post-RTL task almost always causes trouble.
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A Bit About Memory

HBM4 Elevates AI Training Performance To New Heights
With 3D stacking, high bandwidth and capacity can be achieved in a small, pow...
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by Nidish Kamath
Embedded ML Design

Trapped By Legacy
Just bolting a matrix accelerator onto existing processor IP leads to long-te...
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by Steve Roddy
At The Core

Deploying PyTorch Models On Edge Devices
A step-by-step tutorial for enabling fast, efficient inference close to where...
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IP And LP In SoCs

High-Speed Test IO: Addressing High-Performance Data Tran...
Maximize limited package pins with IO that can act as high-speed test ports t...
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by Lakshmi Jain
Everything Low Power

UALink: Powering The Future Of AI Compute
A low-latency, high-bandwidth fabric that supports hundreds of accelerators i...
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by Sangeeta Soni
Power Source

How To Optimize Products For Performance And Sustainability
Incorporating materials, simulations, data management, optimization, and PLM ...
May 15, 2025
by Mehru Singh
Inside Edge AI Processing

NPU Acceleration For Multimodal LLMs
Processing input data from multiple modalities on mobile and embedded devices.
December 12, 2024
by Pat Donnelly
MIPI And Beyond

MIPI In Next Generation Of AI IoT Devices At The Edge
IoT demands a balance between cloud and edge processing to optimize system pe...
April 11, 2024
by Ashraf Takla

Knowledge Centers
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