Systems & Design

Top Stories

Startup Funding: Q1 2025

AI chips and data center communications see big funding; 75 startups raise $2 billion.

Challenges In Managing Chiplet Resources

The chip industry is exploring multiple avenues for simplifying multi-die integration, but difficulties remain for optimizing designs.

Digital Twins For Design And Verification Workflows

Can we model the chip development flow so AI could optimize it?

The Evolving Role Of AI In Verification

Semiconductor verification is changing to integrate AI with human expertise.

Verification Experts Vs. Generalists

The increasing complexity of design is driving specialization and innovative approaches in verification — and some interesting arguments.

Improving Verification Methodologies

The verification problem space is outpacing the speed of the tools, placing an increasing burden on verification methodologies and automation impro...

Lines Blurring Between Supercomputing And HPC

Acceleration of performance improvements due to AI and disaggregation are driving significant changes at the leading edge of computing.

Multi-Die Design Complicates Data Management

Design data and metadata are ballooning, and no one is quite sure how long to save it or what to delete.

Universities Augment Engineering Curricula To Boost Emplo...

Companies need engineers across all disciplines and universities are stepping up to deliver them; schools reap benefits, too.

AI In Data Management Has Limits

Trusting which data to use and what can be deleted still requires human oversight; startups are at a disadvantage.

More Top Stories »



Round Tables

Digital Twins For Design And Verification Workflows

Can we model the chip development flow so AI could optimize it?

The Evolving Role Of AI In Verification

Semiconductor verification is changing to integrate AI with human expertise.

Verification Experts Vs. Generalists

The increasing complexity of design is driving specialization and innovative approaches in verification — and some interesting arguments.

Design Customization Puts Heavy Burden On Verification

Configurability causes an explosion in verification complexity, but the upside is verification engineers are gaining in stature.

RISC-V Profiles Help Conformance

More than just the processor needs to be defined for standard operating systems. Profiles help a little, but still not enough.

More Roundtables »



Multimedia

Optimizing Data Movement In SoCs And Advanced Packages

Managing on-chip data is becoming more challenging in the AI era.

Scenario Coverage In Formal Verification

As complexity of designs increases, so does the need for coverage in context.

Cracking The Memory Wall

How faster data movement can impact overall system performance.

PCIe Over Optics

The benefits and tradeoffs of using optics to move data.

Livelocks And Deadlocks In NoCs

How to prevent complex systems from freezing up.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

A System Perspective

How AI And Connected Workflows Will Close The Verificatio...

The industry needs a fundamental shift in how verification is approached.
March 27, 2025
Intelligent System Design

High-Speed High-Capacity Mixed-Signal Simulation Of Silic...

Verifying the functionality of a full multi-chip system, including digital co...
March 27, 2025
The Next Wave

Unleashing AI Potential Through Advanced Chiplet Architec...

Chiplets are the only viable solution to maintain the annual cadence of hardw...
March 27, 2025
First By Design

Innovating For 6G

Emulation is crucial for testing the performance of 6G systems in real-time c...
March 27, 2025
NoC NoC

Achieving Lower Power, Better Performance, And Optimized ...

As design complexity increases, manual design approaches can struggle to mini...
March 27, 2025
Looking Past The Horizon

Bold Prediction: 50% Of New HPC Chip Designs Will Be Mult...

Advancements in low-latency interconnects, manufacturing processes, and desig...
February 27, 2025
Memory/IO Wall Solutions

AI Infrastructure At A Crossroads

Weighing efficiency gains vs. the scale of personalization.
January 30, 2025
Making Formal Normal

Corner-Case Bug Hunting for RISC-V

Nice to have, or an imperative?
September 30, 2024
The Chiplet Connection

Enabling Innovative Multi-Vendor Chiplet-Based Designs

What makes chiplets so attractive, and why they are essential for future desi...
September 26, 2024
Clock Talk

Droop And Silent Data Corruption

Advanced silicon lifecycle analytics and on-die telemetry are needed to count...
July 25, 2024

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