Systems & Design

Top Stories

Startup Challenges In A Changing EDA World

Without innovation, it may not be possible to fully utilize technological advances.

Startup Funding: Q4 2024

AI chips and interconnects end year on high note; $3 billion for 75 companies.

Top Tech Videos Of 2024

What chip industry engineers watched in 2024.

Strain, Stress In Advanced Packages Drives New Design App...

Heterogenous integration is pushing chip and package designers to consider multi-physics effects as early as the initial architectural planning sta...

Improving Verification Performance

Verification tools are getting faster and capacity is increasing, but they still can't keep up with the problem space. Verification is crossing mor...

SLM Evolves Into Critical Aspect Of Chip Design And Opera...

Silicon lifecycle management applications and techniques are gaining traction as chipmakers figure out how to use them more effectively.

RISC-V Profiles Help Conformance

More than just the processor needs to be defined for standard operating systems. Profiles help a little, but still not enough.

Chip Companies Play Bigger Role In Shaping University Cur...

Design and AI companies are using a range of tools to help graduates become productive more quickly. Some are feeding their requirements directly t...

Top-Down Vs. Bottom-Up Chiplet Design

Third-party chiplets are hitting the market as chiplet models evolve. Who's calling the shots isn't clear yet.

Slow Progress On Generative EDA

The dream may be to have generative AI write RTL, but text is only one of the necessary things AI must understand to help with many design and impl...

More Top Stories »



Round Tables

RISC-V Profiles Help Conformance

More than just the processor needs to be defined for standard operating systems. Profiles help a little, but still not enough.

How AI Is Transforming System Design

LLMs and machine learning are automating expertise in an aging workforce.

RISC-V’s Software Portability Challenge

A hardware-software contract is needed for software portability, but RISC-V is not yet defined well enough to know what that is.

RISC-V Conformance

Finding out if a processor implementation matches the specification is important, but conformance testing is currently not available.

Barriers To Chiplet Sockets

Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time to slow down and make...

More Roundtables »



Multimedia

Distributed Voltage And Frequency Scaling Gaining Traction

More data to process with fewer available knobs to turn are boosting demand for this technique.

The Evolution of HBM

From 2.5D to AI everywhere.

Using Formal For RISC-V Security

Why microarchitectures and custom coding on low-cost chips are a growing source of concern.

Scaling Performance In AI Systems

Tackling bottlenecks and improving time to market in complex designs.

Globally Asynchronous, Locally Synchronous Clocks

Improving performance through better partitioning of data movement in complex designs.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Intelligent System Design

Introduction Of High Bandwidth Embedded USB2v2 (eUSB2v2) ...

A scalable I/O technology specifically designed for inside-the-box asymmetric...
December 19, 2024
The Next Wave

Redefining XPU Memory For AI Data Centers Through Custom ...

A custom implementation of HBM can be a performance differentiator justifying...
December 19, 2024
First By Design

Why Circuit Designers And Test Engineers Need Impedance A...

Understanding the behaviors of materials and components under actual operatin...
December 19, 2024
A System Perspective

Enhancing Power Reliability Through Design-Stage Layout O...

Address issues like IR drop and electromigration early in the design process.
December 19, 2024
NoC NoC

2024 Set The Stage For NoC Interconnect Innovations In So...

The year's advancements in modular scaling, cache coherence, and hardware/sof...
December 19, 2024
Looking Past The Horizon

Achieving Successful Multi-Die Signoff

Multi-die designs require advanced parasitic extraction, power analysis, and ...
December 19, 2024
Memory/IO Wall Solutions

UMI: Extending Chiplet Interconnect Standards To Deal Wit...

Consistently moving data at speeds required for AI systems.
October 14, 2024
Making Formal Normal

Corner-Case Bug Hunting for RISC-V

Nice to have, or an imperative?
September 30, 2024
The Chiplet Connection

Enabling Innovative Multi-Vendor Chiplet-Based Designs

What makes chiplets so attractive, and why they are essential for future desi...
September 26, 2024
Clock Talk

Droop And Silent Data Corruption

Advanced silicon lifecycle analytics and on-die telemetry are needed to count...
July 25, 2024

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

What’s Next For Through-Silicon Vias

Fab tools are being fine-tuned for TSV processes as demand ramps for everything from HBM to integrated RF, power, and MEMS in 3D packaging.

Chip Industry Week in Review

Next-gen EUV laser R&D; $285M CHIPS Act award; U.S. microelectronics research centers; Synaptics-Google deal; maskless microLED DUV; Micron's $2B fab expansion; Tesla sales slump; USB-C mandate in Europe.

Semiconductor Engineering’s Special Reports 2024

A compendium of essential information for the chip industry.

Chip Industry Week In Review

Global semi sales; 3rd CHIPS Act flagship; UFS and memory standards; Chinese military companies in U.S.; TSVs; CES; 18 new fabs; HBM packaging; SDVs; rad tolerance.

Startup Funding: Q4 2024

AI chips and interconnects end year on high note; $3 billion for 75 companies.