RISC-V’s Software Portability Challenge
A hardware-software contract is needed for software portability, but RISC-V is not yet defined well enough to know what that is.
Chiplets Make Progress Using Interconnects As Glue
Industry learning expands as more SoCs are disaggregated at leading edge, opening door to more third-party chiplets.
HW and SW Architecture Approaches For Running AI Models
Custom hardware tailored to specific models can unlock performance gains and energy savings that generic hardware cannot achieve, but there are tra...
RISC-V Conformance
Finding out if a processor implementation matches the specification is important, but conformance testing is currently not available.
Startup Funding: Q3 2024
New startups emerge from stealth; 75 companies raise $2 billion.
Barriers To Chiplet Sockets
Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time to slow down and make...
Using AI To Glue Disparate IC Ecosystem Data
Why the chip industry is so focused on large language models for designing and manufacturing chips, and what problems need to be solved to realize ...
RAG-Enabled AI Stops Hallucinations, Adds Sources
New GenAI method enables better answers and performs more functions.
Pressure Builds To Adopt Virtual Prototypes
Creating complex multi-chiplet systems is no longer a back-of-the-envelope diagram, but viable methodologies are still in short supply.
What Comes After HBM For Chiplets
The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken ...
More Top Stories »
RISC-V’s Software Portability Challenge
A hardware-software contract is needed for software portability, but RISC-V is not yet defined well enough to know what that is.
RISC-V Conformance
Finding out if a processor implementation matches the specification is important, but conformance testing is currently not available.
Barriers To Chiplet Sockets
Perfection sometimes stands in the way of progress, and there is evidence this may be happening with chiplets. It may be time to slow down and make...
What Comes After HBM For Chiplets
The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken ...
Defining The Chiplet Socket
The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?
More Roundtables »
Using Formal For RISC-V Security
Why microarchitectures and custom coding on low-cost chips are a growing source of concern.
Scaling Performance In AI Systems
Tackling bottlenecks and improving time to market in complex designs.
Globally Asynchronous, Locally Synchronous Clocks
Improving performance through better partitioning of data movement in complex designs.
Working With Chiplets
What comes after HBM, and why that matters for future designs.
Data Routing In Heterogeneous Chip Designs
Challenges and solutions for working with multiple chiplets.
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