Mixed Messages Complicate Mixed-Signal
Analog and mixed signal content is adding risk to ASIC designs. Pessimists see the problem getting worse, while optimists point to AI and chiplets ...
Distributing Intelligence Inside Multi-Die Assemblies
Disaggregration requires traffic cops and in-chip monitors to function as expected over time.
Security Vulnerabilities Difficult To Detect In Verificat...
New tools and techniques are being developed and can help keep the verification process secure, alongside a firm foundation of good design verifica...
Can You Build A Known-Good Multi-Die System?
Executive Outlook: Just because the various components in an advanced package work individually and together doesn't guarantee they will work post-...
Optimizing Data Movement
Problems and solutions for improving performance with more data.
A Balanced Approach To Verification
In the past, simulation was the only tool available for verification, but today there are many. Balancing the costs and rewards is not always easy.
Executive Outlook: Chiplets, 3D-ICs, and AI
Trouble spots, and some fixes, for the next wave of high-performance semiconductors.
More Data, More Redundant Interconnects
Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications.
From Tool Agents To Flow Agents
The industry has already demonstrated gains using AI in tight iteration loops, but how does that evolve to cover larger portions of the development...
AI Drives Re-Engineering Of Nearly Everything In Chips
Complexity, uncertainty, and lots of moving pieces will challenge the semiconductor industry for years to come.
Can You Build A Known-Good Multi-Die System?
Executive Outlook: Just because the various components in an advanced package work individually and together doesn't guarantee they will work post-...
Executive Outlook: Chiplets, 3D-ICs, and AI
Trouble spots, and some fixes, for the next wave of high-performance semiconductors.
From Tool Agents To Flow Agents
The industry has already demonstrated gains using AI in tight iteration loops, but how does that evolve to cover larger portions of the development...
AI Agents Need Goals
AI cannot optimize unless it can measure progress towards goals, but defining those goals is not easy, especially when looking at the entire develo...
Digital Twins For Design And Verification Workflows
Can we model the chip development flow so AI could optimize it?
Agentic AI In Chip Design
What comes next after generative AI, and how that will be used in EDA.
Optical Interconnectivity At 224 Gbps
Pros and cons of replacing copper with optical in data-intensive AI systems.
Speeding Up Die-To-Die Interconnectivity
Just adding more or thicker wires to a design isn't sufficient with chiplets.
What’s Changing In SerDes
Faster data movement in AI systems comes at a cost.
Optimizing Data Movement In SoCs And Advanced Packages
Managing on-chip data is becoming more challenging in the AI era.
