Manufacturing, Packaging & Materials

Top Stories

Baby Steps Toward 3D DRAM

Stacking layers means a complete architecture rethink.

Challenges In Powering Electrification With GaN And SiC

No single material is ideal, but unique combinations are emerging.

HBM Options Increase As AI Demand Soars

But manufacturing reliable 3D DRAM stacks with good yield is complex and costly.

FOPLP Gains Traction in Advanced Semiconductor Packaging

Panel-level packaging offers scalability and cost efficiency, but meeting advanced node process targets remains a formidable challenge.

New Tradeoffs In Leading-Edge Chip Design

Monolithic integration builds from the top down and the bottom up.

One Chip Vs. Many Chiplets

Challenges and options vary widely depending on markets, workloads, and economics.

Asia Government Funding Surges

Taiwan, China, South Korea, and Japan continue to foster growth, while the rest of Asia competes for foreign investment and talent.

EMEA Investments Driving Technology Specialization

Semiconductor policies, funding, and competitions are enabling industry and academia to pursue breakthroughs amidst the quest for supply chain resi...

2D Semiconductors Make Progress, But So Does Silicon

Can 2D materials be fabricated consistently at a cost that competes with silicon?

Hybrid Bonding Makes Strides Toward Manufacturability

Companies are selecting preferred flows, but the process details are changing rapidly to meet the needs of different applications.

More Top Stories »



Round Tables

One Chip Vs. Many Chiplets

Challenges and options vary widely depending on markets, workloads, and economics.

Monolithic Vs. Heterogeneous Integration

New processes, materials, and combinations of existing technologies will determine future directions for semiconductors.

Opportunities Grow For GPU Acceleration

The convergence of AI/ML and GPU advancements are creating new opportunities for faster processing.

Navigating The GPU Revolution

Potential cost and time benefits are driving GPU adoption, despite challenges.

Making Heterogeneous Integration More Predictable

Engineering teams, methods, and modeling need to be rethought. One size doesn't fit all, and defects are inevitable.

More Roundtables »



Multimedia

Emerging Technologies Driving Heterogeneous Integration

New architectures, opportunities, and challenges as chipmakers move from monolithic architectures to chiplets.

Secure Movement Of Data In Test

Why heterogeneous integration changes how data is used in manufacturing.

Challenges Of Testing Advanced Packages

Bundling more chips or chiplets increases the difficulty of thoroughly testing a device.

High-NA EUV Progress And Problems

Why it's necessary, when it's coming, and what still needs to be done.

Challenges Of Heterogeneous Integration

Cramming more features into a small space adds challenges and benefits.

More Multimedia »



See All Posts in Manufacturing, Packaging and Materials »

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  Trending Articles

Baby Steps Toward 3D DRAM

Stacking layers means a complete architecture rethink.

What’s Next For Through-Silicon Vias

Fab tools are being fine-tuned for TSV processes as demand ramps for everything from HBM to integrated RF, power, and MEMS in 3D packaging.

Chip Industry Week in Review

Next-gen EUV laser R&D; $285M CHIPS Act award; U.S. microelectronics research centers; Synaptics-Google deal; maskless microLED DUV; Micron's $2B fab expansion; Tesla sales slump; USB-C mandate in Europe.

Strain, Stress In Advanced Packages Drives New Design Approaches

Heterogenous integration is pushing chip and package designers to consider multi-physics effects as early as the initial architectural planning stage; new tools may be needed.

Navigating Increased Complexity In Advanced Packaging

Variability is a growing challenge; achieving higher yields requires even tighter control and precision.