System-Level Design

Top Stories

Partitioning Drives Architectural Considerations

Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning.

Breaking Down The Debug Process

Experts at the Table: Debug is not a monolithic task, and each stage in the processes needs a different focus.

HW/SW Design At The Intelligent Edge

Systems are extremely specific and power-constrained, which makes design extremely complex.

Open Source Processors: Fact Or Fiction?

Calling an open-source processor free isn't quite accurate.

Test Chips Play Larger Role At Advanced Nodes

Opinions diverge about whether to use fewer test chips, or whether to put more diagnostics into those chips.

Debugging Complex SoCs

Experts at the Table, Part 1: Why time spent in debug is increasing, underlying trends, and what surveys do not reveal.

Will Open-Source EDA Work?

DARPA program pushes for cheaper and simpler tools, but it may not be so easy.

CEO Outlook: Rising Costs, Chiplets, And A Trade War

Experts at the Table, Part 2: Opinions vary on China's technology independence and its ability to develop key technology internally.

Training Tomorrow’s Chip Designers

The semiconductor industry partners with academia in a variety of ways to support the next generation of electrical engineers.

CEO Outlook: It Gets Much Harder From Here

Experts at the Table, Part 1: As power/performance benefits shrink at each new node, engineers are turning to different chip architectures and new ...

More Top Stories »



Round Tables

Partitioning Drives Architectural Considerations

Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning.

Breaking Down The Debug Process

Experts at the Table: Debug is not a monolithic task, and each stage in the processes needs a different focus.

Evolution Of Verification Engineers

Experts at the Table, part 3: The role of a verification engineer will change and start to look a lot like knowledge management.

Incremental System Verification

Experts at the table: Part 2. How does a PSS model get verified and who will create that model? What happens when models extend beyond the specific...

When Verification Leads

Experts at the Table, part 1: Would an executable requirements document transform verification or design? Experts have differing ideas.

More Roundtables »



Multimedia

Verification In The Cloud

Why this shift is finally happening.

Analog Fault Simulation

How to improve coverage in safety-critical designs.

Verification At 7/5nm

What's missing for advanced-node SoCs and AI chips.

Safety-Critical Coverage

Verification in automotive, medical and industrial designs.

Billion-Gate Design Connectivity

Dealing with integration issues in large, complex chips.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Rethinking What Goes On A Chip

Shrinking features isn't the only way forward.
June 27, 2019
What Were They Thinking

Moderating A Panel

You need several skills to moderate a panel discussion. Do you have what it t...
Just A Formality

Enabling The RISC-V Ecosystem

Industry initiatives are critical factors for processor family success.
Looking Past The Horizon

Automation And Correct By Construction Will Empower 3D-IC...

SiPs consisting of SoCs and stacked HBMs are promising for AI, HPC, and 5G, b...
A System Perspective

Providing An AI Accelerator Ecosystem

Using high-level synthesis along with IP libraries and toolkits to speed hard...
Frankly Speaking

Intelligent System Design—Why The Future Does Need Us!

Envisioning a whole new level of systems design for the technologies of the f...
Semi Thoughts

Google Cloud—A View From The Top

From cloud computing for chip design to AI for whales and exoplanet discovery.
Intelligent Analytics

DAC 2019 Was About More Than Just Chips

IoT security, artificial intelligence, and cloud EDA were all major themes th...
Design & Verification

Meanwhile, 35 Years Later…

Why SoC hybrid co-emulation for verification of hardware and software is so i...
Programmed Complexity

Challenges In Using HLS For FPGA Design

How to improve productivity in FPGAs while opening them to a broader skill set.
April 29, 2019
Against The Grain

Make-Or-Break Time For Portable Stimulus

We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

5nm Vs. 3nm

Half nodes, different transistor types, and numerous other options are adding uncertainty everywhere.

Will Open-Source EDA Work?

DARPA program pushes for cheaper and simpler tools, but it may not be so easy.

Open Source Processors: Fact Or Fiction?

Calling an open-source processor free isn’t quite accurate.

Will In-Memory Processing Work?

Changes that sidestep von Neumann architecture could be key to low-power ML hardware.

Big Shifts In Big Data

Why the growth of cloud and edge computing and the processing of more data will have a profound effect on semiconductor design and manufacturing.