Systems & Design

Top Stories

Dealing With AI/ML Uncertainty
How neural network-based AI systems perform under the hood is currently unknown, but the industry is finding ways to live with a black box.
Published on April 25th, 2024 by Karen Heyman

Is There Any Hope For Asynchronous Design?
This approach has long held promise, but never managed to deliver. Is there a fundamental problem, or is it just bad luck?
Published on April 25th, 2024 by Brian Bailey

NoCs In 3D Space
The network on chip has become essential for complex designs, but it needs to evolve to support 3D designs and enable the integration of chiplets.
Published on April 3rd, 2024 by Brian Bailey

What’s Missing In 2.5D EDA Tools
While it's possible to create interposer-based systems today, the tools and methodologies are incomplete, and there is a mismatch with organizations.
Published on March 28th, 2024 by Brian Bailey

Interconnects Essential To Heterogeneous Integration
Chiplet communication will be impossible without interconnect protocols.
Published on March 28th, 2024 by Karen Heyman

Engineers Or Their Tools: Which Is Responsible For Findin...
As chips become more complex, the tools used to test them need to get smarter.
Published on March 28th, 2024 by Ann Mutschler and Adam Kovac

3D-IC Intensifies Demand For Multi-Physics Simulation
New challenges are driving big changes throughout the design flow, from tools to job responsibilities.
Published on March 20th, 2024 by Ann Mutschler

Security Is Critical For Commercial Chiplets
Data management, trust, traceability, and provenance tracking are essential to making a chiplet marketplace work.
Published on March 13th, 2024 by Ann Mutschler

Chiplet IP Standards Are Just The Beginning
Data and protocol interoperability standards are needed for EDA tools, and there are more hurdles ahead. Customized chiplets will be required for A...
Published on March 6th, 2024 by Ann Mutschler

Optimizing EDA Cloud Hardware And Workloads
Algorithms written for GPUs can slice simulation time from weeks to hours, but not everything is optimized or benefits equally.
Published on March 4th, 2024 by Aharon Etengoff

More Top Stories »



Round Tables

Engineers Or Their Tools: Which Is Responsible For Findin...
As chips become more complex, the tools used to test them need to get smarter.
Published on March 28th, 2024 by Ann Mutschler and Adam Kovac

Security Is Critical For Commercial Chiplets
Data management, trust, traceability, and provenance tracking are essential to making a chiplet marketplace work.
Published on March 13th, 2024 by Ann Mutschler

Chiplet IP Standards Are Just The Beginning
Data and protocol interoperability standards are needed for EDA tools, and there are more hurdles ahead. Customized chiplets will be required for A...
Published on March 6th, 2024 by Ann Mutschler

Commercial Chiplet Ecosystem May Be A Decade Away
Technology and business hurdles must be addressed before widespread adoption.
Published on February 29th, 2024 by Ann Mutschler

Navigating EDA Vendor Cloud Options
Experts weigh in on the challenges of the cost of cloud, and working with multi-vendor tools in cloud environments.
Published on October 25th, 2023 by Ann Mutschler

More Roundtables »



Multimedia

Challenges In RISC-V Verification
How to debug a multi-core chip and ensure it will be cache coherent and secure.
Published on April 2nd, 2024 by Ed Sperling

Cache Coherency In Heterogeneous Systems
Why maintaining flexibility in coherency is essential in heterogeneous designs.
Published on April 1st, 2024 by Ed Sperling

Integration Challenges For RISC-V Designs
Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
Published on February 27th, 2024 by Ed Sperling

Densification Of RF Designs
Design issues for 5G and 6G wireless communications.
Published on December 20th, 2023 by Ann Mutschler

Improving AI Productivity With AI
How engineers can utilize AI to push more design elements further left.
Published on November 28th, 2023 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

What Were They Thinking

Revitalizing DAC
It is great to see the DAC conference come back to life, but EDA companies ne...
April 25, 2024
by Brian Bailey
A System Perspective

The 3D-IC Multiphysics Challenge Dictates A Shift-Left St...
Gleaning useful information well before all the details of an assembly are kn...
April 25, 2024
by John Ferguson
Making Formal Normal

Verification In Crisis
How can formal verification help?
April 25, 2024
by Ashish Darbari
NoC NoC

The Path Toward Future Automotive EE Architectures
The race to centralized computing.
April 25, 2024
by Frank Schirrmeister
Looking Past The Horizon

How To Get The Most Out Of Gate-All-Around Designs
Co-optimization of foundation IP and design flows for new transistors.
April 25, 2024
by Andrew Appleby
Intelligent System Design

Exploring The Security Framework Of RISC-V Architecture I...
Controlling the access to physical memory addresses.
April 25, 2024
by Anika Sunda
First By Design

How 6G Research Will Revolutionize Mobile Experiences
AI will be used in just about every subsystem of 6G networks.
April 25, 2024
by Ben Coffin
Clock Talk

Staying Within The Margins
Why real-time values are essential for identifying future variations in volta...
March 28, 2024
by Barry Pangrle
Inside Edge AI Processing

Considerations For Accelerating On-Device Stable Diffusio...
The generative AI model that is a critical test for NPU design.
November 30, 2023
by Pat Donnelly
Editor's Note

Which Processor Is Best?
Intel's support for RISC-V marks a technological and cultural shift.
March 1, 2022
by Ed Sperling

Knowledge Centers
Entities, people and technologies explored


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