System-Level Design

Top Stories

EDA Revenue Up 18.9%

PCB and IP buoyed the healthy results for Q4.

Supporting CPUs Plus FPGAs

Experts at the table, part 1: What the toolchain looks like today and the different mindsets within those flows.

Challenges Grow For IP Reuse

Methodologies for integration become a competitive tool as complexity and possible options skyrocket.

Users Talk Back On Standards Process

How does a standard get created? A lot of hard work and balancing different opinions can be frustrating, but that communication is vital.

Carving Up Verification

Cadence's verification chief discusses current best practices for dealing with design complexity.

Embedded FPGAs Come Of Age

These devices are gaining in popularity for more critical functions as chip and system designs become more heterogeneous.

Custom Hardware Thriving

Predictions about software-driven design with commoditized IoT hardware were wrong.

What Does AI Really Mean?

eSilicon's chairman looks at technology advances, its limitations, and the social implications of artificial intelligence—and how it will change ...

Fault Simulation Reborn

A once indispensable tool is making a comeback for different applications, but problems remain to be solved.

Software Modeling Goes Mainstream

More chipmakers turn to software-hardware interaction for performance, power, security.

More Top Stories »



Round Tables

Supporting CPUs Plus FPGAs

Experts at the table, part 1: What the toolchain looks like today and the different mindsets within those flows.

Overcoming The Limits Of Scaling

Experts at the table, part 3: Looking at IP from a system level; the good and bad of advanced packaging; the benefits of machine learning.

Overcoming The Limits Of Scaling

Experts at the table, part 2: The impact of security on architectures, what's missing in software, and why EDA business models are so rigid.

Formal’s Roadmap

Experts at the Table, part 3: The breadth of adoption of formal, technology breakthroughs and the challenges created by machine learning.

Formal’s Roadmap

Experts at the Table, part 2: The need for a formal specification, coverage and progress toward formal verification for analog.

More Roundtables »



Multimedia

Biz Talk: ASICs

eSilicon's CEO discusses the future of scaling, the rollout of advanced packaging, and where the next big opportunities will be.

Tech Talk: Timing Closure

Why timing closure is suddenly a problem again and what to do about it.

Tech Talk: Earlier Software

How to knock a year off software development.

Tech Talk: ADAS

Why the Advanced Driver Assistance Systems standard is so important and where the potential pitfalls are.

Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

When Will It Be Done?

Big chip companies continue to get chips out the door on time, but it's getting ...
What Were They Thinking

What Is Portable Stimulus?

The standard for verification intent modeling has a misleading name. It should b...
Design & Verification

Leveraging The Power Of VDMA Engines For Computer Vision Apps

Part 1: An in-depth overview of FPGA-based use cases for reference designs....
Just A Formality

10 Ways To Skin A Formal Puzzle

Applying formal verification techniques to a classic logic puzzle reveals plenty...

Challenges Grow For IP Reuse

Methodologies for integration become a competitive tool as complexity and possib...

IoT Edge Design Demands A New Approach

A low-cost proof-of-concept is necessary in designing IoT edge devices....

Ubiquitous AI

How to boost performance with the same power envelope....

The CEO Outlook Returns

Trends, opportunities, danger signs, and the future of semiconductor design....

Software Modeling And KPI

Closing the loop with key performance indicators....

Advanced ASICs Are A Team Sport

Open, transparent collaboration among companies is vital for a successful projec...

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2

As verification expands to cover more aspects of system development, application...

ISO 26262 Functional Safety Training Resources

Keep your skills up-to-date to avoid missing automotive opportunities....

Executive Committee Members You Need To Know...

...And your first slate of deadlines....

OSDN – On-chip Software Defined Network

Not just another NoCoff....

The Trust Burning Debug Cycle From Hell

Is my untested code a menace to the team? It gets personal....

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

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As the market for artificial intelligence heats up, so does confusion about how to build these systems.

China: Fab Boom or Bust?

A frenzy of activity is causing lots of speculation about how this complex market will evolve.

Big Data On Wheels

As the market for chips in cars grows, so does the amount of sensor data that needs to be processed.

The Week In Review: Design

Andes IPO; automotive physical IP; energy processing unit; PCIe with AXI bridge; certifications and IP for TSMC 7, 12nm.

Patterning Problems Pile Up

Edge placement error emerges as the top issue at advanced nodes.