System-Level Design

Top Stories

Connecting The Car

ArterisIP's CEO digs into what the connected vehicle will mean for technology, business, and society.

Verification Unification

Experts at the Table, part 2: Strategies for using Portable Stimulus to drive formal and simulation, as well as the common ground with coverage.

RISC-V Pros And Cons

Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

Respecting Reset

Reset is one of the most important signals in a design and yet perhaps one of the least respected. What can go wrong and how to correct it.

Toward Continuous HW-SW Integration

Increased complexity and heterogeneity are prompting new methods that can avert surprises at the end of the design cycle.

Verification Unification

Experts at the Table, part 1: The verification task relies on both dynamic execution and formal methods today, but those technologies have few conn...

Whatever Happened To HLS?

Experts at the table, part 3: Targeting FPGA resources, OpenCL, tackling safety and security issues, addressing IoT needs.

What’s Next In Neural Networking?

Technology begins to twist in different directions and for different markets.

Can Formal Replace Simulation?

Exclusive: Formal leaders discuss the ways in which they are stretching formal tools to the limit to solve an ever-increasing array of tasks.

Speeding Up Neural Networks

Adding more dimensions creates more data, all of which needs to be processed using new architectural approaches.

More Top Stories »



Round Tables

Verification Unification

Experts at the Table, part 2: Strategies for using Portable Stimulus to drive formal and simulation, as well as the common ground with coverage.

Verification Unification

Experts at the Table, part 1: The verification task relies on both dynamic execution and formal methods today, but those technologies have few conn...

Whatever Happened To HLS?

Experts at the table, part 3: Targeting FPGA resources, OpenCL, tackling safety and security issues, addressing IoT needs.

Whatever Happened to High-Level Synthesis?

Experts at the table, part 2: Playing in an IP integration world, defining verification flows and compatibility with a virtual prototype.

Whatever Happened To High-Level Synthesis?

Experts at the table, part 1: What progress has been made in High Level Synthesis and what can we expect in the near future?

More Roundtables »



Multimedia

Tech Talk: ISO 26262

What's new in the automotive standard and how to design cars that can fail safely.

Biz Talk: ASICs

eSilicon's CEO discusses the future of scaling, the rollout of advanced packaging, and where the next big opportunities will be.

Tech Talk: Timing Closure

Why timing closure is suddenly a problem again and what to do about it.

Tech Talk: Earlier Software

How to knock a year off software development.

Tech Talk: ADAS

Why the Advanced Driver Assistance Systems standard is so important and where the potential pitfalls are.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

DAC Exchange

Live From Austin—The DAC Exhibition Floor

A quick overview of three days of activities and what to plan for....
What Were They Thinking

Verification Cowboys

What does it take to be a successful EDA startup? Seven verification company exe...
Editor's Note

Foundry Wars, Take Two

What multiple process nodes and market uncertainties mean to the design world. ...
A View From the Top

Verification And Validation Don't Mean The Same Thing

The two tasks have different goals and require a different approach....
Just A Formality

Formal Verification's Continental Divide

The different ways formal verification is deployed across the world....
Frankly Speaking

Emulation Enabling Automotive Designs

Key components that allow IP development in a cycle accurate SoC context....
Architect's Diary

Boldy Go Where No NoC Has Gone Before

Is achieving functional safety goals without compromising PPA possible?...
A System Perspective

Huawei Delivers Outstandingly Accurate Models

Making sure packages achieve the 'as-designed' thermal performance....
Design & Verification

It's Show Time

Why the past few months are just a blur....
Embedded Software

Capturing The Future, Frame By Frame

A peek at what you'll see next....
Semi Thoughts

Historic FinFET/2.5D Firsts

Like the first trips to space, 2.5D design takes a lot of experimentation and pr...
Guest Blog

The CEO Outlook Returns

Trends, opportunities, danger signs, and the future of semiconductor design....
NoC NoC

ISO 26262 Functional Safety Training Resources

Keep your skills up-to-date to avoid missing automotive opportunities....
Against The Grain

The Trust Burning Debug Cycle From Hell

Is my untested code a menace to the team? It gets personal....

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

RISC-V Pros And Cons

Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

Shrink Or Package?

Advanced packaging shifts to mainstream with complete flows, better tools, market proof points.

NAND Market Hits Speed Bump

Transition from planar to 3D NAND is harder and more time-consuming than expected.

The LiDAR Gold Rush

LiDAR firms attract investments as corporate and venture investors vie for a piece of this burgeoning market.

What’s Next In Scaling, Stacking

The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.