System-Level Design

Top Stories

Verification As A Flow

Experts at the Table, part 2: How did Portable Stimulus get its name, and will it replace UVM?

Design Reuse Vs. Abstraction

IP reuse has reduced the urgency for a higher level of abstraction in complex system-level design, but that still could change.

Verification As A Flow

Experts at the Table, part 1: As more tools are added into the verification flow, how well are they integrated? How well do vendors work together? ...

The Darker Side Of Consolidation

What happens when companies are combined? The outcome often isn't as good as the announcement.

Adding NoCs To FPGA SoCs

As complexity and device sizes rise, so does the need for an on-chip network.

Searching For A System Abstraction

Hardware became stuck using the RTL abstraction, but system-level tasks need more views of hardware than are currently available.

Formal Abstraction And Coverage

What experts in formal verification are saying behind closed doors.

Market And Tech Inflections Ahead

Synopsys Co-CEO Aart de Geus explains why systemic complexity will be the next big challenge, and what that means for EDA and the chip industry.

CEO Outlook On Chip Industry

Part 3: The growing impact of security on design, and where the discontinuities and opportunities will be over the next five years.

IBM Takes AI In Different Directions

What AI and deep learning are good for, what they're not good for, and why accuracy sometimes works against these systems.

More Top Stories »



Round Tables

Verification As A Flow

Experts at the Table, part 2: How did Portable Stimulus get its name, and will it replace UVM?

Verification As A Flow

Experts at the Table, part 1: As more tools are added into the verification flow, how well are they integrated? How well do vendors work together? ...

CEO Outlook On Chip Industry

Part 3: The growing impact of security on design, and where the discontinuities and opportunities will be over the next five years.

CEO Outlook On Chip Industry

Part 2: Concerns grow about ethical choices and liability in AI-based safety-critical systems, and who will be responsible for making those decisions.

CEO Outlook On Chip Industry

Part 1: New opportunities and potential pitfalls in automotive, 5G, connected intelligence and infrastructure as a service in EDA.

More Roundtables »



Multimedia

ISO 26262 Statistics

Tech Talk: The statistical underpinnings of safety standards.

Emulation-Driven Implementation

Tech Talk: How to improve confidence that designs will work properly in less time.

Tech Talk: Traceability In Functional Safety

Regulations, standards and liability.

Tech Talk: FPGA RTL Checking

How to make sure the RTL in an FPGA matches what you developed.

Tech Talk: Improving Verification

How to deal with different use cases in complex designs.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

Toward Cross-Layer Resilience

Reliability is no longer just about one chip, or even one device.
June 28, 2018
What Were They Thinking

Abstraction Aging

Do engineers find comfort in details as they get older, and is abstraction fo...
A System Perspective

Raising The Bar On Flat CDC Verification With Hierarchica...

Capturing the CDC intent of any block as a data model that can be seamlessly ...
Just A Formality

The Skies Over EDA Are Finally Cloudy

What took the industry so long to become comfortable with cloud-based tools?
Design & Verification

SoC FPGAs And HW/SW Co-Simulation

Verifying the interaction between programmable logic and processing earlier i...
Semi Thoughts

FinFET ASICs: It Takes A Platform

Utilizing IP relevant to a pre-specified chip architecture to boost design pr...
Frankly Speaking

DAC 2018: System Design, Cloud And Machine Learning

How accurate were predictions about interoperable models and designing in the...
Looking Past The Horizon

First Look At USB 3.2

Demonstrating a USB 3.2 host and device operating together at full speed.
May 24, 2018
NoC NoC

Neural Nets In ADAS And Autonomous Driving SoC Designs

Why interconnects are vital when incorporating deep learning into automotive ...
April 26, 2018
Intelligent Analytics

Bugs With Long Tails Can Be Costly Pests

In the world of servers and HPC, the smallest of inefficiencies can build int...
Architect's Diary

Looking For The Elephant In The Valley

Female role models doing exceptional things in tech have always existed. Hope...
March 27, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Big Trouble At 3nm

Costs of developing a complex chip could run as high as $1.5B, while power/performance benefits are likely to decrease.

Quantum Computing Becoming Real

Technology has the potential to reshape processing everywhere, starting with limited scientific and commercial applications.

Security Holes In Machine Learning And AI

A primary goal of machine learning is to use machines to train other machines. But what happens if there’s malware or other flaws in the training data?

Bridges Vs. Interposers

Momentum growing for low-cost alternatives to interposers as a way of reducing overall development costs.

The Darker Side Of Consolidation

What happens when companies are combined? The outcome often isn’t as good as the announcement.