System-Level Design

Top Stories

EDA Revenue Up 6.6% For Q2

AI, automotive and design activity by systems companies continue to drive EDA industry growth.

IP’s Growing Impact On Yield And Reliability

Managing IP quality and compatibility is becoming more difficult at advanced nodes and in safety-critical markets.

New Technologies To Support 3D-ICs

Experts at the Table: 3D design and packaging is creating new demand on tools and requires a tight ecosystem and sharing across the industry.

EDA Gears Up For 3D

Experts at the Table: What are the limitations today that are preventing 3D-ICs from becoming mainstream, and which companies pushing to make it ha...

Synthesizing Hardware From Software

Can a software engineer create hardware? It may be possible, but not in the way that existing high-level synthesis tools do it.

What Is A Custom Processor?

The definition has changed, and so has the impact on the design process.

Siemens-Mentor Deal Retrospective

CEO Tony Hemmelgarn talks about autonomous cars, 5G, EDA integration and the Siemens acquisition of Mentor.

Debug Tools Are Improving

Experts at the Table: How is machine learning going to impact debug, and what other improvements are on tap with debug?

Are Digital Twins Something For EDA To Pursue?

Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem.

Hardware-Software Co-Design Reappears

There may be a second chance for co-design, but the same barriers also may get in the way.

More Top Stories »



Round Tables

New Technologies To Support 3D-ICs

Experts at the Table: 3D design and packaging is creating new demand on tools and requires a tight ecosystem and sharing across the industry.

EDA Gears Up For 3D

Experts at the Table: What are the limitations today that are preventing 3D-ICs from becoming mainstream, and which companies pushing to make it ha...

Debug Tools Are Improving

Experts at the Table: How is machine learning going to impact debug, and what other improvements are on tap with debug?

Are Digital Twins Something For EDA To Pursue?

Part one: Defining the digital twins concept; the trouble with models; the issue with the ecosystem.

Partitioning Drives Architectural Considerations

Experts at the Table, part 3: Systems of subsystems; heterogeneous systems; re-partitioning.

More Roundtables »



Multimedia

Signoff-Compatible CDC

Why netlist clock domain crossing is now an essential complement to RTL CDC at advanced nodes and in AI chips.

Verification In The Cloud

Why this shift is finally happening.

Analog Fault Simulation

How to improve coverage in safety-critical designs.

Verification At 7/5nm

What's missing for advanced-node SoCs and AI chips.

Safety-Critical Coverage

Verification in automotive, medical and industrial designs.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Just A Formality

Chip Security Needs A New Language

SystemVerilog assertions can nicely capture many hardware requirements. Howev...
August 26, 2019
Editor's Note

Surround And Conquer

Why large chip companies are embracing third-party accelerators—and trying ...
August 22, 2019
What Were They Thinking

Making Security User Friendly

Device manufacturers need to show how secure their devices are, while making ...
A System Perspective

Fast LFD Flows With Pattern Matching And Machine Learning...

Ways to observe the impact of systematic process variation on layouts to impr...
Looking Past The Horizon

Clock Domain Crossing Signoff Through Static-Formal-Simul...

A coverage-driven hybrid approach of static and dynamic verification for func...
Intelligent Analytics

Responsibility And Automotive Security

It's time for the automotive industry to come together to define security bes...
Frankly Speaking

Verification Requirements For 5G To Enable A Perfect Stor...

From fixed wireless access to mission-critical devices, new 5G applications r...
July 25, 2019
Semi Thoughts

Memory IP: From Cobblestone To Cornerstone

Embedded memory started as a foundational element in chip design and has now ...
Programmed Complexity

Optimize MATLAB C/C++ Code For HLS

The design flow steps used to convert C/C++ algorithms to a hardware implemen...
Design & Verification

Meanwhile, 35 Years Later…

Why SoC hybrid co-emulation for verification of hardware and software is so i...
June 27, 2019
Against The Grain

Make-Or-Break Time For Portable Stimulus

We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
October 25, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Chiplets, Faster Interconnects, More Efficiency

Why Intel, AMD, Arm, and IBM are focusing on architectures, microarchitectures, and functional changes.

Nvidia’s Top Technologists Discuss The Future Of GPUs

Power, performance, architectures, and making AI pervasive.

Siemens-Mentor Deal Retrospective

CEO Tony Hemmelgarn talks about autonomous cars, 5G, EDA integration and the Siemens acquisition of Mentor.

Synthesizing Hardware From Software

Can a software engineer create hardware? It may be possible, but not in the way that existing high-level synthesis tools do it.

Advanced Packaging Options Increase

But putting multiple chips into a package is still difficult and expensive.