System-Level Design

Top Stories

Custom Hardware Thriving

Predictions about software-driven design with commoditized IoT hardware were wrong.

What Does AI Really Mean?

eSilicon's chairman looks at technology advances, its limitations, and the social implications of artificial intelligence—and how it will change ...

Fault Simulation Reborn

A once indispensable tool is making a comeback for different applications, but problems remain to be solved.

Software Modeling Goes Mainstream

More chipmakers turn to software-hardware interaction for performance, power, security.

2017: Tool And Methodology Shifts

Second of two parts: System definition to drive tool development, with big changes expected in functional verification.

Hybrid Simulation Picks Up Steam

Using a combination of simulation and emulation can be beneficial to an SoC design project, but it isn't always easy.

Changing Direction In Chip Design

This year's Kaufman Award winner digs into scaling issues, industry fragmentation, and what semiconductor designs will look like over the next deca...

Architect Specs Harder To Follow

Each new node adds uncertainties and problems, especially at 7nm. Interdisciplinary communication becomes essential.

What’s Missing In Advanced Packaging

When it comes to multi-board and multi-chips-on-a-board designs, do engineers have all the tools they need?

Tools For Heterogeneous System Development

Final in a series: The amount of software that interacts with hardware is increasing, and no longer can applications ignore the execution platform....

More Top Stories »



Round Tables

Overcoming The Limits Of Scaling

Experts at the table, part 3: Looking at IP from a system level; the good and bad of advanced packaging; the benefits of machine learning.

Overcoming The Limits Of Scaling

Experts at the table, part 2: The impact of security on architectures, what's missing in software, and why EDA business models are so rigid.

Formal’s Roadmap

Experts at the Table, part 3: The breadth of adoption of formal, technology breakthroughs and the challenges created by machine learning.

Formal’s Roadmap

Experts at the Table, part 2: The need for a formal specification, coverage and progress toward formal verification for analog.

Formal’s Roadmap

Experts at the Table, part 1: Panelists look at the progress made by formal in the past five years and where we can expect to see new capabilities ...

More Roundtables »



Multimedia

Tech Talk: Timing Closure

Why timing closure is suddenly a problem again and what to do about it.

Tech Talk: Earlier Software

How to knock a year off software development.

Tech Talk: ADAS

Why the Advanced Driver Assistance Systems standard is so important and where the potential pitfalls are.

Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

Tech Talk: ISO 26262

What can go wrong in designing to this automotive standard.

More Multimedia »



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Latest Blogs

Editor's Note

AI Storm Brewing

The acceleration of artificial intelligence will have big social and business im...
What Were They Thinking

Could DVCon Be Better?

Just one idea about how DVCon could be improved and the impact it could have on ...
Design & Verification

Better Code With RTL Linting And CDC Verification

A simple but effective way to find bugs in ASIC and FPGA designs....
A System Perspective

IP Qualification During RTL Synthesis

New physical synthesis technologies can help mitigate IP development risks....
A View From the Top

Software Modeling And KPI

Closing the loop with key performance indicators....
Semi Thoughts

Advanced ASICs Are A Team Sport

Open, transparent collaboration among companies is vital for a successful projec...
Frankly Speaking

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2

As verification expands to cover more aspects of system development, application...
Just A Formality

Find Your Way To San Jose Next Week… For DVCon, Of Course!

This year's program is stacking up to be an insightful and educational four days...
Guest Blog

Happy 25th Birthday, HAL!

AI has come a long way since HAL became operational....
NoC NoC

ISO 26262 Functional Safety Training Resources

Keep your skills up-to-date to avoid missing automotive opportunities....
Embedded Software

Constructing The Pillars Of The ARM HPC Ecosystem

Alternative HPC architectures will only happen if a strong supporting software e...
DAC Exchange

Executive Committee Members You Need To Know...

...And your first slate of deadlines....
Architect's Diary

OSDN – On-chip Software Defined Network

Not just another NoCoff....
Against The Grain

The Trust Burning Debug Cycle From Hell

Is my untested code a menace to the team? It gets personal....
Design & Verification

The Problem With CDCs

And how it affects your DO-254 project...
Knowledge Central

Major Growth For Knowledge Center

An update on the Knowledge Center, plus a few pop quizzes....

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

What Are FeFETs?

How this new memory stacks up against existing non-volatile memory.

Battling Fab Cycle Times

Why it’s taking longer to manufacture chips at 10/7nm and what can be done about it.

New Memories And Architectures Ahead

So far there is not widespread adoption, but many see change as inevitable.

What’s New In Connected Autos

Internet of Things technology will be crucial to automobiles, but connectivity comes at a price.

Betting On Wafer-Level Fan-Outs

Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.