System-Level Design

Top Stories

Prototypes Proliferate

What will it take to make hardware prototyping as ubiquitous as emulation?

System Coverage Undefined

What does it mean to have verified a system and how can risk be measured? The industry is still scratching its head.

Verifying AI, Machine Learning

OneSpin's CEO looks at what's needed in this computing space, which technologies are winning, and what the key metrics will be.

Verification’s Breaking Points

Depending on design complexity, memory allocation or a host of other issues, a number of approaches simply can run out of steam.

Integrated Photonics

Experts at the Table, part 3: What is the role of EDA in building photonics systems, is a viable IP market developing and how are photonics systems...

Executive Insight: Lip-Bu Tan

Cadence's CEO digs into machine learning, advanced packaging, and the shift from chip design to system design.

Executive Insight: Wally Rhines

Mentor’s CEO looks at consolidation, what’s behind the Siemens acquisition, and the big opportunity in system design and integration.

Tools To Design CNNs

If neural networking architectures are simpler than a CPU, why is it so difficult to create them?

What’s New At Hot Chips

Neuromorphic computing and machine learning dominate the leading edge of chip design this year.

Portable Stimulus Status Report

The Early Adopter release of the first new language in 20 years is under review as the deadline approaches.

More Top Stories »



Round Tables

Integrated Photonics

Experts at the Table, part 3: What is the role of EDA in building photonics systems, is a viable IP market developing and how are photonics systems...

Integrated Photonics

Experts at the Table, part 2: What can be done to reduce costs and improve packaging options, and what makes sense in terms of fabrication technolo...

Integrated Photonics

Experts at the Table, part 1: Are we there yet? Where is the demand coming from and which types of product will drive innovation?

Hybrid Emulation

Experts at the Table, part 2: Finding the right balance of performance, visibility, turn-around time and verification objectives.

Verification Unification

Experts at the Table, part 3: Power, safety and security—and how Portable Stimulus and formal can help with all of these.

More Roundtables »



Multimedia

Tech Talk: TCAM

How to save power and reduce area with ternary content addressable memory.

Tech Talk: DO-254

A look at the safety-critical standard for aerospace and what it means for automotive electronics.

Tech Talk: ISO 26262

What's new in the automotive standard and how to design cars that can fail safely.

Biz Talk: ASICs

eSilicon's CEO discusses the future of scaling, the rollout of advanced packaging, and where the next big opportunities will be.

Tech Talk: Timing Closure

Why timing closure is suddenly a problem again and what to do about it.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

What Were They Thinking

Getting A Standard Right The First Time

Is the Accellera Portable Stimulus Standard ready to be released? What are the p...
Against The Grain

Generically Reusable IP No One Uses

If we just keep putting generically reusable on the box, all we’re doing is se...
Editor's Note

Thinking Much Bigger

Why system-level design is about to get a huge boost. ...
Frankly Speaking

System Design And Verification Challenges: Are They On- Or Off-Chip?

What's next for system integration?...
A System Perspective

Get To Know The Gate-Level Power Aware Simulation

Using Liberty libraries to accumulate cell-level attributes and power down funct...
A View From the Top

Prototyping Building Blocks

How putting together LEGOs is like building an SoC....
Design & Verification

Finite State Machine Synthesis In Programmable Circuits

Why PLDs are so critical for low-power devices, and how to optimize them....
Embedded Software

Making Software Development Equivalent For Models And Boards

Using the same software images for virtual and FPGA prototyping....
Semi Thoughts

Talking The Talk On Training

An intensive training program for finFET ASIC design....
Just A Formality

DVCon Europe Takes Over Munich October 16-17

Formal and functional safety feature at this year's event....
Architect's Diary

The Race To Autonomous Cars

It's a relay, not a sprint....
NoC NoC

Avoiding Traffic Jams In SoC Design

The real value in planning interconnects may not be obvious until after the chip...
Guest Blog

IoT Security Requirements Ramping

Government and industry groups begin ramping up efforts to limit breaches....
Research: SLD

System Bits: Aug. 8

4D camera; AI sleep monitoring; learning to run....
DAC Exchange

Live From Austin—The DAC Exhibition Floor

A quick overview of three days of activities and what to plan for....

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

What Happened To ReRAM?

After years of delays, this next-gen memory is finally gaining traction.

Looming Issues And Tradeoffs For EUV

New lithography tools will be required at 5nm, but pellicles, resists and uptime are still problematic.

Unsolved Litho Issues At 7nm

Computational challenges on the rise with EUV. Scanners are no longer interchangeable.

What’s Next for the IoT?

Industrial IoT now dominates the market, but confusion is still rampant in all sectors.

IoT Cyber-Security: A Missing Piece Of The Smart City Puzzle

How to protect devices in a smart city from a wide range of cyber threats.