System-Level Design

Top Stories

The Impact of Domain Crossing on Safety

Experts at the Table, part 3: What addition problems does this create in application areas, such as automotive? When will we see more automated sol...

The Impact of Moore’s Law Ending

Chips will cost more to design and manufacture even without pushing to the latest node, but that's not the whole story.

What Makes A Good AI Accelerator

Optimizing processor architectures requires a broader understanding data flow, latency, power and performance.

EDA Cloud Adoption Hits Speed Bumps

What problems are prohibiting semiconductor design moving into the Cloud? Steps are being taken to overcome them.

From Physics To Applications

eSilicon's CEO zeroes in on the impact of AI and advanced packaging on ASIC design.

Cloud Drives Changes In Network Chip Architectures

New data flow, higher switch density and IP integration create issues across the design flow.

Is Cloud Computing Suitable for Chip Design?

Semiconductor design lags behind other industries in adopting the cloud, but there could be some good reasons for that. Change is difficult.

Betting Big On Discontinuity

Mentor's CEO looks at the impact of AI and machine learning, what's after Moore's Law, and the surge in EDA and semiconductors.

Processing In Memory

Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.

Using More Verification Cores

Experts at the Table, part 3: How has the software industry been dealing with parallelization. What can we learn from them and what can we teach them?

More Top Stories »



Round Tables

The Impact of Domain Crossing on Safety

Experts at the Table, part 3: What addition problems does this create in application areas, such as automotive? When will we see more automated sol...

So Many Waivers Hiding Issues

Experts at the Table, part 2: Domain crossings can produce thousands of waivers. How does a team put in place a methodology for dealing with them?

Domain Crossing Nightmares

Experts at the Table, part 1: How many domain crossings exist in a typical SoC today and when is the right time to verify their correctness?

Using More Verification Cores

Experts at the Table, part 3: How has the software industry been dealing with parallelization. What can we learn from them and what can we teach them?

Partitioning Drives Architectural Considerations

Experts at the Table, part 1: When and how do chip architects prioritize partitioning?

More Roundtables »



Multimedia

Building AI SoCs

How to develop AI chips when algorithms are changing so quickly.

Using High-Bandwidth Memory

Tech Talk: Designing for high-throughput computing.

Planning Out Verification

Connecting the pieces in the verification flow.

Thermal Impact On Reliability At 7/5nm

Planning shifts further left at advanced nodes due to proximity effects and variation.

Energy-Efficient AI

How to improve the energy efficiency of AI operations.

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Editor's Note

The Race To Design Larger Systems

The semiconductor industry finally is getting the chance to prove itself on a...
October 25, 2018
What Were They Thinking

Reduction In First Silicon Success

Verification costs are contained, but at what cost to success rates? Mentor's...
Against The Grain

Make-Or-Break Time For Portable Stimulus

We hear a lot from vendors about the new Portable Stimulus Standard, but how ...
Just A Formality

Integrating Results And Coverage From Simulation And Formal

Getting a unified project-level view of verification status.
Looking Past The Horizon

Implementing Mathematical Algorithms In Hardware For Arti...

Offload neural network operations from the processor with optimized hardware ...
A System Perspective

Improving Library Characterization Quality And Runtime Wi...

Increasingly specialized process technologies mean it's time to look at new l...
Semi Thoughts

High-Speed Serial Comms: Getting There Is Half The Fun

Cables help open a new dimension of backplane design for data center and 5G i...
Frankly Speaking

The Power Of Ecosystems At Arm TechCon 2018

Major partnership announcements make it clear collaboration is the way forwar...
Design & Verification

Giving Cars A Bird’s-Eye View

How to build an automotive vision monitoring system using FPGAs.
September 27, 2018
Intelligent Analytics

Bugs With Long Tails Can Be Costly Pests

In the world of servers and HPC, the smallest of inefficiencies can build int...
April 26, 2018
Architect's Diary

Looking For The Elephant In The Valley

Female role models doing exceptional things in tech have always existed. Hope...
March 27, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

The Impact of Moore’s Law Ending

Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.

AI Begins To Reshape Chip Design

Technology adds more granularity, but starting point for design shifts as architectures cope with greater volumes of data.

A Crisis In DoD’s Trusted Foundry Program?

GlobalFoundries’ decision to put 7nm on hold is raising concerns across the mil/aero industry.

Carmakers To Chipmakers: Where’s The Data?

Different perspectives and needs create friction as more advanced electronics are added into vehicles.