System-Level Design

Top Stories

Processing In Memory
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Published on September 5th,  2018 by Ed Sperling

Using More Verification Cores
Experts at the Table, part 3: How has the software industry been dealing with parallelization. What can we learn from them and what can we teach them?
Published on August 30th,  2018 by Brian Bailey

Partitioning Drives Architectural Considerations
Experts at the Table, part 1: When and how do chip architects prioritize partitioning?
Published on August 29th,  2018 by Ann Steffora Mutschler

Is Software Necessary?
Hardware has a love-hate relationship with software, especially when it comes to system-level verification. When is software required, and when doe...
Published on August 27th,  2018 by Brian Bailey

Gaps In Verification Metrics
Experts from Arm, Intel, Nvidia and AMD look at what's missing from verification data and how to improve it.
Published on August 23rd,  2018 by Ann Steffora Mutschler

Bugs That Kill
Behind closed doors: Semiconductor executives talk about the bugs they fear the most and the problems solving them.
Published on August 23rd,  2018 by Brian Bailey

Do Parallel Tools Make Sense?
Experts at the Table, part 2: What can be done instead? And why are companies reluctant to do more in the cloud?
Published on August 10th,  2018 by Brian Bailey

Agile Standards
Standards development has changed from defining everything that might be nice, to a more Agile-like development process.
Published on August 8th,  2018 by Brian Bailey

Faster Verification With AI, ML
With engines improving, the design ecosystem is looking to new approaches to improve productivity.
Published on August 1st,  2018 by Ann Steffora Mutschler

Debug Issues Grow At New Nodes
Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly ...
Published on July 26th,  2018 by Ann Steffora Mutschler

More Top Stories »



Round Tables

Using More Verification Cores
Experts at the Table, part 3: How has the software industry been dealing with parallelization. What can we learn from them and what can we teach them?
Published on August 30th,  2018 by Brian Bailey

Partitioning Drives Architectural Considerations
Experts at the Table, part 1: When and how do chip architects prioritize partitioning?
Published on August 29th,  2018 by Ann Steffora Mutschler

Do Parallel Tools Make Sense?
Experts at the Table, part 2: What can be done instead? And why are companies reluctant to do more in the cloud?
Published on August 10th,  2018 by Brian Bailey

Faster Verification With AI, ML
With engines improving, the design ecosystem is looking to new approaches to improve productivity.
Published on August 1st,  2018 by Ann Steffora Mutschler

Why Parallelization Is So Hard
Experts at the Table, part 1: Are we looking to solve the wrong problems? Where does parallelization work best and why.
Published on July 30th,  2018 by Brian Bailey

More Roundtables »



Multimedia

Energy-Efficient AI
How to improve the energy efficiency of AI operations.
Published on August 30th,  2018 by Ed Sperling

Changing The Design Flow
The rationale for fusing together various pieces of a digital design.
Published on August 7th,  2018 by Ed Sperling

High-Speed SerDes At 7nm
What's changing inside of data centers and how does it affect chip design?
Published on July 30th,  2018 by Ed Sperling

Will FPGAs Work As Expected?
Why equivalence checking is so critical for this market.
Published on July 27th,  2018 by Ed Sperling

M2M’s Network Impact
Why new architectures are required as machines begin talking to machines.
Published on July 25th,  2018 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Looking Past The Horizon

It’s All About Staying Ahead Of The Test Challenges...
As test pattern compression falls behind, new techniques are needed to keep t...
September 11, 2018
by Steve Pateras
Editor's Note

Architects Firmly In Control
New chips show multiple levels of innovation, with AI thrown in.
August 23, 2018
by Ed Sperling
What Were They Thinking

Hiring And Firing
When does it improve a project to take someone off of it?
by Brian Bailey
A System Perspective

Digital IC Bring-Up With A Bench-Top Environment
The process of test pattern bring-up, debug, and device characterization is r...
by Matthew Knowles
Just A Formality

Demystifying EDA Support For ISO 26262 Tool Qualification
Engineers developing auto chips need clear information, but some EDA vendors ...
by Sergio Marchese
Frankly Speaking

Verification Trends Enabling A 5G Future
5G devices, low power, system of systems, and architecture are key verificati...
by Frank Schirrmeister
Design & Verification

Accessing Registers With UVM-RAL
Directly access registers by name from the testbench, without having to know ...
by Sunil Sahoo
Semi Thoughts

Technical Conferences: The Insurmountable Opportunity
The number of new markets makes it difficult to choose between an expanding a...
July 26, 2018
by Mike Gianfagna
Intelligent Analytics

Bugs With Long Tails Can Be Costly Pests
In the world of servers and HPC, the smallest of inefficiencies can build int...
April 26, 2018
by Gajinder Panesar
Architect's Diary

Looking For The Elephant In The Valley
Female role models doing exceptional things in tech have always existed. Hope...
March 27, 2018
by Kavya Ram Mohan
Against The Grain

Abstracting Abstracter Abstractions In Functional Verific...
With the upcoming Portable Stimulus standard, we need to consider whether abs...
March 26, 2018
by Neil Johnson

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

GF Puts 7nm On Hold

Foundry forms ASIC subsidiary as it focuses on 14nm/12nm and above.

by Mark LaPedus

Processing In Memory

Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.

by Ed Sperling

People Vs. Self-Driving Cars

Why auto tech companies are so concerned about interactions with humans.

by Susan Rambo

Intel’s Next Move

Company’s push into deep learning opens door to a variety of new architectures, including tiles, advanced packaging and more customized solutions.

by Ed Sperling

Variation In Low-Power FinFET Designs

Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.

by Ann Steffora Mutschler

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2018 SMG   |  Terms of Service  |  Privacy Policy