UCIe Goes Back To The Drawing Board
The open chiplet interconnect protocol faces some formidable challenges, but progress continues.
Building CFETs With Monolithic And Sequential 3D
Area benefits are significant for future transistor shrinks, but manufacturing challenges remain.
Tackling Variability With AI-based Process Control
How AI is being used in the fab today, and what's coming in the future.
Chip Ecosystem Apprenticeships Help Close The Talent Gap
Registered apprenticeships, community colleges, and in-house training can help build a broad workforce pipeline for technician roles and more advan...
Published on February 12th, 2024 by
Liz Allan
Fan-Out Panel-Level Packaging Hurdles
The economics look attractive, but first the industry needs convergence on panel size, process tools, and materials.
Many More Hurdles In Heterogeneous Integration
More resources will be needed for IC-to-package design, process extendibility, and improved reliability.
Navigating Heat In Advanced Packaging
New approaches and materials being explored as chip industry pushes into heterogeneous integration.
3D Integration Supports CIM Versatility And Accuracy
Solving compute-in-memory's limitations requires new approaches and dimensions.
Money Pours Into New Fabs And Facilities
Investments boom as countries and companies vie for supply chain security and technology leadership.
Fabs Begin Ramping Up Machine Learning
New models can debug processes and boost yield, but there are lots of caveats.
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Making Heterogeneous Integration More Predictable
Engineering teams, methods, and modeling need to be rethought. One size doesn't fit all, and defects are inevitable.
What Can Go Wrong In Heterogeneous Integration
Workflows and tools are disconnected, mechanical stress is ill-defined, and complete co-planarity is nearly impossible. But there are solutions on ...
Heterogeneous Integration Finding Its Footing
Definitions, applications, and tools are still evolving, but success stories are becoming more common.
Data Management Challenges In Heterogeneous Systems
Who owns the data, how to secure it, and who can monetize it still need to be resolved.
Need To Share Data Widens In IC Manufacturing
But access must be limited to relevant data, particularly for leading-edge designs and advanced packaging.
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Challenges Of Testing Advanced Packages
Bundling more chips or chiplets increases the difficulty of thoroughly testing a device.
High-NA EUV Progress And Problems
Why it's necessary, when it's coming, and what still needs to be done.
Challenges Of Heterogeneous Integration
Cramming more features into a small space adds challenges and benefits.
Challenges In Packaging 5G And 6G
From package-defined antennas to antenna-defined packages, and lots of tradeoffs in between.
How Curvilinear Mask Writing Affects Chip Design
The impact of curved shapes on design rules and manufacturability.
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