Week In Review: Manufacturing, Test


Packaging and test In the rankings, ASE was the top OSAT in terms of sales in the first quarter of 2019, according to TrendForce. Amkor and JCET were next in the rankings. “Judging from the falling phone sales 1Q19 impacted by the U.S.-China trade dispute and the oversupply situation in memory markets, the total revenue of the top ten businesses in packaging and testing are predicted to st... » read more

The Arm-Huawei Disconnect


Arm's move to stop licensing its processor IP to HiSilicon, the captive chipmaker for Huawei, has set off a panic across the semiconductor industry. While the underlying threat to the entire chip industry is very real, many of the conclusions being drawn about this move are misleading or just plain wrong. When the U.S. government blacklisted Huawei, it imposed export restrictions on shipping... » read more

Impact Of U.S.-China Trade War


The trade war between the United States and China is escalating and it is here to stay. Last year, the Trump administration started the trade war with China for basically two reasons. First, China has a massive trade surplus with the U.S. Second, U.S. companies have been the subject of IP theft in China, which has largely gone unchecked, according to the Trump administration. Many disagre... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing


As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

Multifunctional Materials Enable Single-Layer Temporary Bonding And Debonding


Many new wafer-level packaging (WLP) technologies involve the processing of thin wafers that must be mechanically supported during the manufacturing flow. These technologies include fan-out wafer-level packaging (FOWLP), fan-in wafer-level chip-scale packaging (FI-WLCSP), 3-D FOWLP, 2.5-D integration with interposer technology, and true 3-D IC integration using through-silicon via (TSV) interco... » read more

Improved Accuracy And Robustness For Advanced DRAM With Tunable Multi-Wavelength Imaging Scatterometry Overlay Metrology


By Honggoo Lee, Sangjun Han, Minhyung Hong, Jieun Lee, Dongyoung Lee, Ahlin Choi and Chanha Park of SK Hynix, and Dohwa Lee, Seongjae Lee, Jungtae Lee, Jeongpyo Lee, DongSub Choi, Sanghuck Jeon, Zephyr Liu, Hao Mei, Tal Marciano, Eitan Hajaj, Lilach Saltoun, Dana Klein, Eran Amit, Anna Golotsvan, Wayne Zhou, Eitan Herzl, Roie Volkovich and John C. Robinson of KLA. Abstract Overlay process c... » read more

Q1 2019 Unit Drop Impacts Wafer Demand For 2019


The Semico Wafer Demand Model update for Q1 2019 now results in a 5.9% decline in wafer demand for 2019. Along with process technology and productivity, Semico’s Wafer Demand Model is highly dependent on semiconductor unit sales. In the Q1 2019, total semiconductor units dropped by 7.4% compared to Q4 2018 and 3.8% compared to Q1 2018. The drop in units is significant because of the broad spe... » read more

Small Critical Subsystems Suppliers Outperform In Downturns


Clouds continue to persist over the semiconductor supply chain with little sign of lifting. In March, the decline in week-over-year chip sales appeared to be slowing, providing a glimmer of hope for the beginning of a new cycle. However, the recent rapid escalation of the tariff war between the U.S. and China heaped more uncertainty on the industry and visibility continues to remain low. Rev... » read more

SiC Demand Growing Faster Than Supply


The silicon carbide (SiC) industry is in the midst of a major expansion campaign, but suppliers are struggling to meet potential demand for SiC power devices and wafers in the market. In just one example of the expansion efforts, Cree plans to invest up to $1 billion to increase its SiC fab and wafer capacities. As part of the plan, Cree is developing the world’s first 200mm (8-inch) SiC f... » read more

Partitioning In 3D


The best way to improve transistor density isn't necessarily to cram more of them onto a single die. Moore’s Law in its original form stated that device density doubles about every two years while cost remains constant. It relied on the observation that the cost of a processed silicon wafer remained constant regardless of the number of devices printed on it, which in turn depended on litho... » read more

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