category: Manufacturing, Packaging and Materials

category: Auto, Security & Edge AI

Creating A Moore’s Law For AI Scaling
By Laura Peters - 24 Jun, 2026 - Comments: 0

Key Takeaways: AI scalability will require full-stack co-optimization, not just bigger data centers. AI workloads require a 10X compute efficiency gain over 10 years, making collaboration across algorithms, architectures, devices, packaging, and communication fabrics essential to deliver a 10X improvement in compute efficiency over the next decade.  Edge AI chips are moving to leadi... » read more

Mask Economics Shape High-NA EUV Adoption
By Gregory Haley - 22 Jun, 2026 - Comments: 0

Key Takeaways: Mask costs are not stopping leading-edge scaling, but they increasingly influence design, node, and process choices. High-NA EUV will tighten requirements for CD, EPE, local CDU, mask 3D modeling, stitching, and materials. Reduced depth of focus in High-NA EUV will drive new resist, etch, film, and absorber approaches. Experts at the table: Semiconductor Engin... » read more

Scaling ADAS To 10+ Cameras
By WonBae Bang - 18 Jun, 2026 - Comments: 0

By WonBae Bang, KiDong Sim, Weilung Lu, and Adrian Arcedera Introduction Advanced Driver Assistance Systems (ADAS) are increasingly adopted by automotive manufacturers to enhance driving safety. These systems help drivers in the driving process, thereby increasing car and road safety. ADAS technologies include features such as adaptive cruise control, lane departure warning and automatic emer... » read more

Accelerating GAA Logic Yield Optimization With Digital Twins
By Qingpeng Wang - 18 Jun, 2026 - Comments: 0

  Digital twins allow engineers to minimize costly wafer experiments by simulating the entire GAA logic process upfront Machine learning applied to virtual data simultaneously reduces multiple critical failure modes, boosting yield from 1.6% to 87.2% This methodology offers a repeatable, cost-efficient path to accelerate advanced node manufacturing as device complexity grows... » read more

How To Build Billions of Bumps
By Bryon Moyer - 18 Jun, 2026 - Comments: 0

Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

VLSI 2026: Intel 18A Platform Momentum From Devices To Routed Designs
By Lori Scott - 18 Jun, 2026 - Comments: 0

Intel Foundry’s process technology roadmap is powered by innovations that are enabling customers to build increasingly capable products for the artificial intelligence (AI) era. At the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, Intel Foundry presented progress on a number of important aspects of our front-end silicon process innovations. This includes Intel 18A-P featurin... » read more

A New Fracture Engine For Curvilinear Masks And MULTIGON Mask Data
By Travis Brist - 18 Jun, 2026 - Comments: 0

Curvilinear masks are rapidly moving into high-volume production. This transition is driven by the need for better pattern fidelity, larger wafer process windows, and more effective use of inverse lithography technology (ILT) and curvilinear optical proximity correction (OPC). However, curvilinear masks also create a new challenge for mask data preparation (MDP): when curvilinear MULTIGON patte... » read more

Randomizing Wafers To Zero In On Process Problems Much Faster
By Errol Akomer - 18 Jun, 2026 - Comments: 0

Randomizing wafers to enable slot-positional analysis is essential for detecting root causes of problems , you had to purchase additional sorters and expensive specialized software. That typically requires additional resources – operators, engineers, and IT. In addition, you had to accept some cycle time reduction because of the extra processing and handling that was needed. Randomization ... » read more

How to Create Efficient Bump and TSV Plans for Multi-Die Designs
By Synopsys - 18 Jun, 2026 - Comments: 0

In a multi-die design logical and physical interconnectivity between dies (or a die and interposer or other substrate) is achieved through microbumps or hybrid bonding pads between contacting dies. Today’s multi-die designs can have hundreds of thousands or millions of bumps, and this number will be increasing dramatically in the future, as hybrid bonding technology greatly reduces the pi... » read more

Automated 310mm Panel-Level Packaging to Accelerate AI Innovation: Tech Brief
By ASE - 18 Jun, 2026 - Comments: 0

This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency. The larger panel format supports higher throughput, reduced cycle time, and lower cost per package, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC applic... » read more

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