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Packaging, Test & Materials

Top Stories

Defect Challenges Growing In Advanced Packaging

Spotting defects with existing inspection tools is getting harder, but upgrading to new technology is expensive.

Lab-To-Fab Testing

Test vendors are trying to build a bridge between verification and automated test in manufacturing.

Automakers Take On More Responsibility

Carmakers shake up supply chain with their own test and system-level integration strategies.

Auto Chip Design, Test Changes Ahead

Which tools and methodologies will work best to ensure electronics operate for extended periods of time under harsh conditions?

The Race To Zero Defects

Complexity, scaling and economics are hindering test engineers from finding all of the faults.

Cobalt Shortages Ahead

Growth in electric vehicles and batteries is causing supply issues that could affect broad swaths of the electronics market.

Sorting Out Packaging Options

Experts at the Table, Part 1: Better naming conventions will reduce confusion over different packaging types, while cost, applications and standard...

Old Vs. New Packages

Two packaging technologies are making microchips smaller and more durable.

The Chiplet Race Begins

DARPA and a number of major vendors are backing this modular approach, but hurdles remain.

Return Of The Organic Interposer

Lower-cost options gain attention as chipmakers seek alternatives for 2.5D packaging.

More Top Stories »



Round Tables

Sorting Out Packaging Options

Experts at the Table, Part 1: Better naming conventions will reduce confusion over different packaging types, while cost, applications and standard...

New 5G Hurdles

Experts at the Table, part 2: Getting 5G standards and technology ready are only part of the problem. Reducing latency and developing applications ...

Preparing For A 5G World

Experts at the table, part 1: Rising costs, massive complexity, and challenges in testing and simulating these devices will require some fundamenta...

2.5D Surprises And Alternatives

Cost and supply chain issues remain as advanced packaging begins to ramp.

Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.

More Roundtables »



Multimedia

5G Test And Deployment

How test will change as next-gen wireless evolves toward higher frequencies.

Variability In Chip Manufacturing

Why consistency in materials is so critical at advanced nodes.

Printed Electronics Materials

Why printed electronics are finding their way into edge devices, and why materials choices are so critical.

Defect Reduction At 7/5nm

Tech Talk: How materials impact quality and yield.

Tech Talk: 5G Everywhere

Where 5G works, where it doesn't, and why it's essential for so many markets.

More Multimedia »



See All Posts in Packaging and Test »

Latest Blogs

Editor's Note

Why Test Costs Will Increase

New materials, applications and packaging are changing the economics of testi...
October 8, 2018
Riding The Silicon Rapids

Collaboration And Advanced Substrates

Many companies have requirements that don't fit neatly into the CMOS roadmap.
Chiplet Connection

How Much Data Can Be Pushed Through Copper Wires?

Pushing toward the Shannon signaling capacity using less energy consumption.
The Human Machine Interface

Thinking Ahead To Society 5.0

Artificial intelligence is here, and it's already helping make lives better.
Material Science

Solving Fan-Out Wafer-Level Warpage Challenges Using Mate...

Improving technologies that enable heterogeneous integration.
September 10, 2018
All About Test

What’s in a Name?

Test Vision 2020 may need a new moniker.
August 6, 2018
Accelerating Design & Test

Toward Project-Based Learning

The value of student-centered instruction over an extended period of time.
May 7, 2018
The Connected Perspective

2017: A Good Year for ATE

Test equipment sales were up, and so were the share prices of ATE stocks.
January 8, 2018
Inside Big Data

Is It Safe To Assume That All “Passed” Die Ar...

Detecting tricky test escapes and preventing defective parts from getting int...
October 9, 2017
EDA For Manufacturability

Crossing The Chasm: Uniting SoC And Package Verification

EDA companies, OSATs, and foundries must collaborate to ensure wafer-level pa...
March 6, 2017

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

Power Delivery Affecting Performance At 7nm

Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.

RISC-V Inches Toward The Center

Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.

Machine Learning Shifts More Work to FPGAs, SoCs

SoC bandwidth, integration expand as data centers use more FPGAs for machine learning.

EUV Pellicle, Uptime And Resist Issues Continue

Problems won’t derail next-gen litho, but could limit use and affect schedules.