Packaging, Test & Electronic Systems

Top Stories

Time For Massively Parallel Testing

Increasing demand for system-level testing brings changes.

2.5D, FO-WLP Issues Come Into Focus

Advanced packaging goes mainstream, creating ripples throughout the back-end of the semiconductor industry.

How Testing MEMS, Sensors Is Different

These devices require more than an electrical input and output.

Electroplating IC Packages

Tooling challenges increase as advanced packaging ramps up.

MEMS: Improving Cost And Yield

Second in a series: New packaging options could help boost profitability, but testing and thermal issues remain problematic.

Quality Issues Widen

Rising complexity, diverging market needs and time-to-market pressures are forcing companies to rethink how they deal with defects.

2.5D Adds Test Challenges

Advanced packaging issues in testing interposers, TSVs.

What Next For OSATs

ASE's COO opens up on the future of fan-out, growth prospects, and where the next opportunities will show up.

OSAT Biz: Growth And Challenges

Dizzying number of options emerge, but cost remains key factor.

Chip-Package-Board Issues Grow

Success will depend on new tools, a better understanding of who's responsible, and new methodologies for getting designs out the door more quickly.

More Top Stories »



Round Tables

2.5D Surprises And Alternatives

First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.

Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.

Stacked Die Changes

Experts at the table, part 2: Different coefficients of thermal expansion cause warpage problems; known good die issues.

Stacked Die Changes

Experts at the table, part 1: There are new and better options for packaging chips together as the semiconductor industry begins to figure out what...

More Roundtables »



Multimedia

Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

Tech Talk: 14nm And Stacked Die

Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.

Tech Talk: 2.5D Stacked Die

What's the real motivation behind stacking die?

More Multimedia »



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Latest Blogs

Editor's Note

Time For New Rules

Trying to fit everything into a discussion about Moore's Law is getting ridiculo...
The Connected Perspective

Looking Back at Board Test

The market has seen change and consolidation....
Inside Big Data

Is Product Quality Getting Lost In The IIoT?

Big data is a necessary tool for cultivating product quality DNA, from the chip ...
Accelerating Design & Test

Getting Ready For 5G

How the RF/microwave industry is changing to deal with the next generation of co...
EDA For Manufacturability

Crossing The Chasm: Uniting SoC And Package Verification

EDA companies, OSATs, and foundries must collaborate to ensure wafer-level packa...

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Great Machine Learning Race

Chip industry repositions as technology begins to take shape; no clear winners yet.

HBM Upstages DDR In Bandwidth, Power

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

22nm Process War Begins

High price of moving to finFETs pushes foundries to offer a less expensive alternative.

LiDAR Completes Sensing Triumvirate

Technology will complement cameras and radar in autonomous vehicles.

Moore’s Law: A Status Report

The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.