Packaging, Test & Electronic Systems

Top Stories

MEMS: Improving Cost And Yield

Second in a series: New packaging options could help boost profitability, but testing and thermal issues remain problematic.

Quality Issues Widen

Rising complexity, diverging market needs and time-to-market pressures are forcing companies to rethink how they deal with defects.

2.5D Adds Test Challenges

Advanced packaging issues in testing interposers, TSVs.

What Next For OSATs

ASE's COO opens up on the future of fan-out, growth prospects, and where the next opportunities will show up.

OSAT Biz: Growth And Challenges

Dizzying number of options emerge, but cost remains key factor.

Chip-Package-Board Issues Grow

Success will depend on new tools, a better understanding of who's responsible, and new methodologies for getting designs out the door more quickly.

Betting On Wafer-Level Fan-Outs

Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.

Logic Analyzers Never Die

But these traditional debugging instruments are taking on different forms now.

What’s Missing In Advanced Packaging

When it comes to multi-board and multi-chips-on-a-board designs, do engineers have all the tools they need?

Making 2.5D, Fan-Outs Cheaper

Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.

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Round Tables

2.5D Surprises And Alternatives

First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.

Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.

Stacked Die Changes

Experts at the table, part 2: Different coefficients of thermal expansion cause warpage problems; known good die issues.

Stacked Die Changes

Experts at the table, part 1: There are new and better options for packaging chips together as the semiconductor industry begins to figure out what...

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Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

Tech Talk: 14nm And Stacked Die

Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.

Tech Talk: 2.5D Stacked Die

What's the real motivation behind stacking die?

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Latest Blogs

Editor's Note

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EDA companies, OSATs, and foundries must collaborate to ensure wafer-level packa...
Inside Big Data

Addressing Test Time Challenges

Improving test strategies is key to cutting costs....
Accelerating Design & Test

ATO 2017: Driven by Necessity

Technology Convergence in the Automotive Industry...

Knowledge Centers
Entities, people and technologies explored

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Big Data On Wheels

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Patterning Problems Pile Up

Edge placement error emerges as the top issue at advanced nodes.

The Week In Review: Design

Andes IPO; automotive physical IP; energy processing unit; PCIe with AXI bridge; certifications and IP for TSMC 7, 12nm.