Packaging, Test & Electronic Systems

Top Stories

OSAT Biz: Growth And Challenges

Dizzying number of options emerge, but cost remains key factor.

Chip-Package-Board Issues Grow

Success will depend on new tools, a better understanding of who's responsible, and new methodologies for getting designs out the door more quickly.

Logic Analyzers Never Die

But these traditional debugging instruments are taking on different forms now.

What’s Missing In Advanced Packaging

When it comes to multi-board and multi-chips-on-a-board designs, do engineers have all the tools they need?

Making 2.5D, Fan-Outs Cheaper

Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.

2.5D Surprises And Alternatives

First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.

Packaging Wars Begin

OSATs and foundries begin to ramp offerings and investments in preparation for mainstream multi-chip architectures.

Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.

Gaps Emerge In Test Flows

Increasing analog content, more complexity and silos are making test much more difficult.

New Drivers For Test

Pressure is mounting to reduce test costs, while automotive is demanding more ability for circuits to test themselves. Could this unsettle existing...

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Round Tables

2.5D Surprises And Alternatives

First of two parts: Cost and supply chain issues remain as advanced packaging begins to ramp.

Stacked Die Changes

Experts at the table, part 3: How mature are high-speed interconnects and what hurdles remain for widespread adoption.

Stacked Die Changes

Experts at the table, part 2: Different coefficients of thermal expansion cause warpage problems; known good die issues.

Stacked Die Changes

Experts at the table, part 1: There are new and better options for packaging chips together as the semiconductor industry begins to figure out what...

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Multimedia

Tech Talk: 2.5D Issues

How ready is this packaging approach and what problems remain?

Tech Talk: 14nm And Stacked Die

Why the 14nm node will be long lived, and how it will be used in 2.5D and 3D-IC packages.

Tech Talk: 2.5D Stacked Die

What's the real motivation behind stacking die?

More Multimedia »



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  Trending Articles

What Are FeFETs?

How this new memory stacks up against existing non-volatile memory.

Battling Fab Cycle Times

Why it’s taking longer to manufacture chips at 10/7nm and what can be done about it.

New Memories And Architectures Ahead

So far there is not widespread adoption, but many see change as inevitable.

What’s New In Connected Autos

Internet of Things technology will be crucial to automobiles, but connectivity comes at a price.

Betting On Wafer-Level Fan-Outs

Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.