Shrink Or Package?

By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Chip Test Shifts Left

By Jeff Dorsch - 07 Jun, 2017 - Comments: 0

“Shift left” is a term traditionally applied to software testing, meaning to take action earlier in the V-shaped time line of a project. It has recently been touted in electronic design automation and IC design, verification, and test. “Test early and test often” is the classic maxim of software testing. What if that concept could also be implemented in semiconductor testing, to redu... » read more

Focus Shifts To System Quality

By Ed Sperling - 05 Jun, 2017 - Comments: 0

For the past decade, many semiconductor industry insiders predicted that software would take over the world and hardware would become commoditized. The pendulum seems to have stopped, and if anything, it is reversing course. Initial predictions were based on several advantages for software. First, software is easier to modify and patch. Second, universities turn out far more software develop... » read more

Security Issues Up With Heterogeneity

By Ann Steffora Mutschler - 05 Jun, 2017 - Comments: 0

The race toward heterogeneous designs is raising new security concerns across the semiconductor supply chain. There is more IP to track, more potential for unexpected interactions, and many more ways to steal data or IP. Security is a difficult problem no matter what kind of chip is involved, and it has been getting worse as more devices, machines and systems are connected to the Internet. B... » read more

Listening To The Voice Of Your Product

By Optimal Plus - 05 Jun, 2017 - Comments: 0

Much has been said and written about the business values of the Industrial Internet of Things (IIoT). Through connecting the manufacturing elements (machines) on the factory floor, and collecting and analyzing their data, manufacturers can significantly improve the efficiency and profitability of their operations through intelligent predictive maintenance of equipment and optimal equipment ut... » read more

Massively Parallel System-Level Testing

By Astronics - 05 Jun, 2017 - Comments: 0

Decades of advances in the semiconductor industry continue to drive an insatiable consumer demand for smaller, more powerful, more ubiquitous devices – whether in our cars, on our countertops or around our wrists. To meet this demand now and into the future, the fabrication of increasingly complex semiconductor systems for an incredible spectrum of applications must scale accordingly. Additio... » read more

What’s Next In Scaling, Stacking

By Mark LaPedus - 05 Jun, 2017 - Comments: 9

An Steegen, executive vice president of semiconductor technology and systems at [getentity id="22217" e_name="Imec"], sat down with Semiconductor Engineering to discuss IC scaling, chip stacking, packaging and other topics. Imec is an R&D organization in Belgium. What follows are excerpts of that conversation. SE: Chipmakers are shipping 16nm/14nm processes with 10nm and 7nm technologies... » read more

Board Level Reliability Improvement In eWLB

By STATS ChipPAC - 05 Jun, 2017 - Comments: 0

When it comes to reducing form-factor and increasing functional integration of mobile devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP (FOWLP), it is a more optimal and promising solution compared to fan-in WLP because it can offer greater flexibilit... » read more

A More Efficient Way To Calculate Device Specs Of Thousands Of Tests For Improved Quality And Yield

By Guy Cortez - 05 Jun, 2017 - Comments: 0

Today’s devices are required to pass thousands of parametric tests prior to being shipped to customers. A key challenge test engineers face, in addition to optimizing the number of tests they run on the device, is how to quickly and accurately define the true specification limits that should be used to determine if the device is “good”. Device specification limits that are too wide may... » read more

Tech Talk: System In Package

By Ed Sperling - 05 Jun, 2017 - Comments: 0

ASE fellow and senior technical advisor William Chen talks about advanced packaging options and why they are now so important. » read more

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category: Packaging and Test

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