2.5D, Fan-Out Inspection Issues Grow


As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, [getkc id="82" kc_name="2.5D"] and [getkc id="42" kc_name="3D-IC"], along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moo... » read more

Advanced Packaging Goes Mainstream


The roadmap for shrinking digital logic will continue for at least the next 10 years. For others devices, particularly analog, it will slow down or end. And therein lies one of the most fundamental changes in semiconductor design and manufacturing in the past half century. This is no longer just talk. Apple is using a fan-out architecture in its iPhone 7. Memory makers are stacking NAND and ... » read more

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package


Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) count is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targe... » read more

Wireless Test: Too Many Protocols


Testing wireless communications is getting far more difficult as more markets begin adding wireless communications and standards groups push to improve the speed, power and security of existing protocols. There is already a long list of protocols, and it's growing further as new communications technologies are added into the mix. With the addition of 5G, the new 802.11ax standard, and other ... » read more

Finally, Realizing The Full Benefits Of Parallel Site-To-Site (S2S) Testing


A very common and well-known practice by manufacturers during the IC test process is to test as many of the device die or packaged parts as possible in parallel (i.e. sites) during wafer sort and final test in order to increase test time efficiency and lower overall test costs. The constraints that typically restrict how many test sites can be used at any given time are the design I/O and capac... » read more

Wirebond Technology Rolls On


Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types. Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto... » read more

Intel Inside The Package


Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

IIoT Analytics


Founded in 1995, Marvell Technology Group Ltd. has operations worldwide and more than 7,000 employees. A leading fabless semiconductor company, Marvell ships over one billion chips a year. Marvell’s expertise in microprocessor architecture and digital signal processing, drives multiple platforms including high volume storage solutions, mobile and wireless, networking, consumer and green pr... » read more

Improving 5G


The Challenge: By 2020, Cisco forecasts that 5.5 billion people will own mobile phones. In the United Kingdom alone, tens of millions of these mobile users will each consume 20 GB of data per month and use more than 25 different smart devices in their daily routines. Factor in data-hungry applications like 4K video, driverless vehicles, smart factories, and broadband access expanding to the mos... » read more

Time For Massively Parallel Testing


Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory devices and other semiconductors, test equipment vendors have resorted to parallel testing technology, simultaneously testing multiple chips at a time. The industry also is turning to system-level tes... » read more

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