Low Power-High Performance

Top Stories

Maintaining Power Profiles At 10/7nm

Capturing what is driving power in a design means different things to different teams, but it's essential at 10nm and below.

Power Challenges At 10nm And Below

Dynamic power density and rising leakage power becoming more problematic at each new node.

Closing The Loop On Power Optimization

Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to ac...

Analog’s Unfair Disadvantage

In a world that favors digital circuitry, analog has increasingly had to cope with processes that have become less favorable to them. But that may ...

Cloud Computing Chips Changing

As cloud services adoption soars, datacenter chip requirements are evolving.

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budg...

The Problem With Clocks

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?

Managing Voltage Drop At 10/7nm

Building a power delivery network with the low implementation overhead becomes more problematic at advanced nodes.

Electric Vehicles Set The Pace

Developments in this part of the market will define low power and energy efficiency for years to come.

HBM Upstages DDR In Bandwidth, Power

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

More Top Stories »



Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »



Multimedia

Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Power Reduction

Why getting granular about energy can yield huge savings and how to utilize idle time.

Tech Talk: Lower Power Embedded NVM

How to increase the battery life in low power devices.

Tech Talk: Power Emulation

Using hardware-assisted verification to tackle complex power issues in SoC design.

More Multimedia »



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Latest Blogs

Editor's Note

The Future Of Sports Cars

A switch to autonomous vehicles could happen more quickly than anyone thought. S...
Power Awareness

Power Just One Piece Of The Puzzle At 10nm And Below

Dynamic power density and rising leakage power make it more important than ever ...
Everything Low Power

The Efficiency Problem

Part 2: Solving Power Limitations for CNNs on DSP Processors ...
A Bit About Memory

The SerDes – Terabit Ethernet Connection

Ethernet is moving faster than ever, presenting a distinct set of challenges for...
At The Core

Voice Recognition’s Role In Safer, More Secure Car Design

Making voice recognition work in the car requires getting the best of both local...
IP And LP In SoCs

Building One Interface Subsystem For Multiple IoT SoCs

Adding flexibility to a design by supporting multiple protocols in an interface ...
Best Of Both: LP & HP

Calibre Evolves Constantly

Why some EDA tools have kept the top spot for over a decade....
Power Source

Design For Silicon Success At 7nm

Rising complexity and tighter design margins increase the cost, and likelihood, ...
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?

Power integrity optimization can no longer be a reactive step in the backend pro...
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Intel Inside The Package

Mark Bohr opens up on the company’s push into multi-chip solutions, and upcoming issues at 7nm and 5nm.

What’s Next In Neural Networking?

Technology begins to twist in different directions and for different markets.

Moore’s Law: Toward SW-Defined Hardware

Part 2: Heterogeneity and architectures become focus as scaling benefits shrink; IP availability may be problematic.

200mm Crisis?

Demand is up, capacity is flat. A look at what’s behind this imbalance.

Extending EUV Beyond 3nm

Now that EUV is finally shipping, companies are working on extending it much further using anamorphic lenses and high numerical aperture technology.