Low Power-High Performance

Top Stories

Power Optimization Strategies Widen

Different markets are heading in different directions, raising questions about whether the chip industry can effectively respond to all of those de...

System-Level Power Modeling Takes Root

Why modeling power much earlier has suddenly become so critical for so many applications.

Does Power Verification Work?

Verification implies comparison against an expected result, but the industry has yet to define how this works for power. How are power bugs found?

Designing 5G Chips

The next-gen wireless technology is riddled with problems, but that hasn't slowed the pace of development.

What Happened To UPF?

Did the power intent standard miss the mark, or is it quietly being adopted? It's hard to tell.

Processing Moves To The Edge

Definitions vary by market and by vendor, but an explosion of data requires more processing to be done locally.

High-Performance Memory Challenges

Capacity, speed, power and cost become critical factors in memory for AI/ML applications.

Mesh Networking Grows For ICs

Approach is yet another way to scale SoCs and systems, but it also adds new level of complexity.

How To Choose The Right Memory

Different types and approaches can have a big impact on cost, power, bandwidth and latency.

Why All Nodes Won’t Work

Cost of porting tools and IP will limit choices at partial nodes and create confusion at others.

More Top Stories »

Round Tables

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

Power Modeling And Analysis

Experts at the Table, part 1: Are power models created early enough to be useful, and is that the best approach?

IP Challenges Ahead

Part 2: For the IP industry to remain healthy it has to constantly innovate, but it's getting harder.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

More Roundtables »


Tech Talk: HBM vs. GDDR6

A look at two different memory options, and the pros and cons of each.

Tech Talk: Shrink Vs. Package

Tradeoffs between putting everything onto a single chip and different advanced packaging options.

Tech Talk: Analog Simplified

Why it's so critical to speed up analog design across a broad swath of markets, and how to get there.

Tech Talk: Electrical Overstress

How to plan for electrical overstress and aging at advanced nodes and in safety-critical designs.

Tech Talk: 7/5/3nm Signoff

How to make sure that advanced node designs will work as planned.

More Multimedia »

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Latest Blogs

At The Core

Cure The Common Cold…

...And much more. A call for papers for Arm TechCon.
May 23, 2018
Electromagnetic Crosstalk

Electromagnetic Crosstalk Considerations In Low Power Des...

A method for shrinking the size and power of designs, with less margin and fe...
May 19, 2018
Editor's Note

Higher Performance, Lower Power Everywhere

New compute models will require significant improvements in both speed and ef...
May 10, 2018
Spotlight On Reliability

Multiphysics Challenges For EDA Tools

Demand for analog electronics is growing, making it increasingly important to...
A Bit About Memory

Deep Learning Neural Networks Drive Demands On Memory Ban...

Bandwidth, not compute power, is emerging as the major bottleneck in many AI ...
Power Source

Early Chip-Package-System Thermal Analysis

Why it's so important to model self-heat effects and junction temperature var...
Best Of Both: LP & HP

Optimizing Your DRC Debug Can Reap Big Productivity Gains

For effective DRC, designers need to optimize not only debugging itself, but ...
IP And LP In SoCs

Developing ASIL Ready SoCs For Self-Driving Cars

Advances in neural networks, coupled with rapidly improving cameras and funct...
Everything Low Power

Where The Rubber Hits The Road: Implementing Machine Lear...

Moving from high-power, high-performance to low-power, high-performance.
Let's Talk PVT Monitoring

Supply Monitoring On 28nm & FinFET: The Challenges P...

Analysis of power consumption and IR drop should happen as part of the design...
April 12, 2018
Power Awareness

Heterogeneous Hubbub

The combination of heterogenous architectures and RISC-V is encouraging new t...
March 8, 2018

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

Packaging Chips For Cars

Why packaging is becoming increasingly critical and difficult in the automotive market.

Designing Hardware For Security

Most attacks in the past focused on gaining access to software, but Meltdown and Spectre have changed that forever.

Next EUV Issue: Mask 3D Effects

Old problem is becoming more difficult to resolve at each new node; mitigation measures being developed.

RF SOI Wars Begin

5G is driving up demand for both 300mm and 200mm capacity. Both are in short supply.

200mm Fab Crunch

Shortages of used equipment and lower margins mean this problem isn’t getting solved anytime soon.