Low Power-High Performance

Top Stories

Modeling On-Chip Variation At 10/7nm
Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.
Published on June 14th,  2017 by Ann Steffora Mutschler

Transient Power Problems Rising
At 10/7nm, power management becomes much more difficult; old tricks don't work.
Published on June 8th,  2017 by Ann Steffora Mutschler

Hardware/Software Tipping Point
Has the tide turned from increasing amounts of general purpose, software defined products, to one where custom hardware will make a comeback?
Published on June 8th,  2017 by Brian Bailey

Maintaining Power Profiles At 10/7nm
Capturing what is driving power in a design means different things to different teams, but it's essential at 10nm and below.
Published on May 17th,  2017 by Ann Steffora Mutschler

Power Challenges At 10nm And Below
Dynamic power density and rising leakage power becoming more problematic at each new node.
Published on May 11th,  2017 by Ann Steffora Mutschler

Closing The Loop On Power Optimization
Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to ac...
Published on May 11th,  2017 by Brian Bailey

Analog’s Unfair Disadvantage
In a world that favors digital circuitry, analog has increasingly had to cope with processes that have become less favorable to them. But that may ...
Published on May 11th,  2017 by Brian Bailey

Cloud Computing Chips Changing
As cloud services adoption soars, datacenter chip requirements are evolving.
Published on April 19th,  2017 by Ann Steffora Mutschler

The Hunt For A Low-Power PHY
The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budg...
Published on April 17th,  2017 by Brian Bailey

The Problem With Clocks
Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?
Published on April 13th,  2017 by Brian Bailey

More Top Stories »



Round Tables

Optimization Challenges For 10nm And 7nm
Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.
Published on September 6th,  2016 by Brian Bailey

The Future Of Memory
Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.
Published on August 24th,  2016 by Ed Sperling

Optimization Challenges For 10nm And 7nm
Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...
Published on August 17th,  2016 by Brian Bailey

Optimization Challenges For 10nm And 7nm
Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.
Published on August 11th,  2016 by Brian Bailey

Mixed-signal/Low-power Design
Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.
Published on August 3rd,  2016 by Jeff Dorsch

More Roundtables »



Multimedia

Tech Talk: 7nm Power
Dealing with thermal effects, electromigration and other issues at the most advanced nodes.
Published on June 19th,  2017 by Ed Sperling

Tech Talk: Neural Networks
How to design and implement convolution neural networks, and what to watch out for.
Published on June 8th,  2017 by Ed Sperling

Tech Talk: Power Signoff
A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.
Published on September 8th,  2016 by Ed Sperling

Tech Talk: Micro-Architecting Power
A deep dive into how to save power by leveraging idle time.
Published on September 7th,  2016 by Ed Sperling

Tech Talk: Power Reduction
Why getting granular about energy can yield huge savings and how to utilize idle time.
Published on June 1st,  2016 by Ed Sperling

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Age Of Acceleration
Focus shifts from the fastest processors to faster processes. ...
by Ed Sperling
Power Awareness

ESD Guns, Transients And Testing…Oh My!
Sometimes a shock to the system is a good thing....
by Ann Steffora Mutschler
A Bit About Memory

From SerDes Chiplets To Die-To-Die Interfaces
As demand for higher bandwidth within a similar power envelope grows, so does th...
by Mohit Gupta
Everything Low Power

What Does “Low Power Optimization” Mean To You?
Different power concerns lead to different solutions....
by Dave Pursley
IP And LP In SoCs

The Evolution Of Deep Learning For ADAS Applications
Advances in embedded vision are powering autonomous driving....
by Gordon Cooper
At The Core

Large-Screen Compute Transformation Is Here
A new chapter is beginning for mobile devices....
by Sriram Ragunathan
Best Of Both: LP & HP

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation
Understanding the Liberty syntax and other non-standard behavioral model librari...
by Progyna Khondkar
Power Source

Design For Silicon Success At 7nm
Rising complexity and tighter design margins increase the cost, and likelihood, ...
by Annapoorna Krishnaswamy
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?
Power integrity optimization can no longer be a reactive step in the backend pro...
by Tobias Bjerregaard
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue
10nm heads into full swing, with 7nm and 5nm on the horizon....
by Barry Pangrle

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

RISC-V Pros And Cons

Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

by Ann Steffora Mutschler

Samsung Unveils Scaling, Packaging Roadmaps

Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.

by Ed Sperling

Shrink Or Package?

Advanced packaging shifts to mainstream with complete flows, better tools, market proof points.

by Ed Sperling

The LiDAR Gold Rush

LiDAR firms attract investments as corporate and venture investors vie for a piece of this burgeoning market.

by Jeff Dorsch

What’s Next In Scaling, Stacking

The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.

by Mark LaPedus

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