Low Power-High Performance

Top Stories

Dealing With System-Level Power

New tools, standards, languages and methodologies will be necessary to automate growing challenges at all process nodes.

IoT Myth Busting

How cost-sensitive are IoT edge devices, what are the real drivers for this industry, and what is the impact on EDA and IP?

Is The IP Industry Healthy?

First of two parts: IP has grown to become the largest segment of EDA revenue, but is it sustainable?

Modeling On-Chip Variation At 10/7nm

Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.

Transient Power Problems Rising

At 10/7nm, power management becomes much more difficult; old tricks don't work.

Safety Plus Security: A New Challenge

First in a series: There is a price to pay for adding safety and security into a product, but how do you assess that and control it? The implicatio...

Hardware/Software Tipping Point

Has the tide turned from increasing amounts of general purpose, software defined products, to one where custom hardware will make a comeback?

Maintaining Power Profiles At 10/7nm

Capturing what is driving power in a design means different things to different teams, but it's essential at 10nm and below.

Power Challenges At 10nm And Below

Dynamic power density and rising leakage power becoming more problematic at each new node.

Closing The Loop On Power Optimization

Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to ac...

More Top Stories »

Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »


Tech Talk: ADAS

What will change in automotive design on the road to autonomous vehicles.

Tech Talk: 7nm Power

Dealing with thermal effects, electromigration and other issues at the most advanced nodes.

Tech Talk: Neural Networks

How to design and implement convolution neural networks, and what to watch out for.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

More Multimedia »

See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Performance To The People

Sending most of the data to the cloud doesn't work. Now what? ...
Power Awareness

Who's Responsible For Transistor Aging Models?

Foundries must provide the basis to predict reliability because every process is...
Best Of Both: LP & HP

Estimating Power And Performing Optimization

Emulation can help deliver the signal visibility necessary for trustable power a...
A Bit About Memory

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law

How the scaling of memory bandwidth and capacity keeps system performance improv...
At The Core

How The Evolution Of SoC Design Is Igniting Innovation Again

While consolidation continues among traditional semiconductor vendors, a wave of...
IP And LP In SoCs

Using An Integrated Subsystem To Accelerate Data Fusion In Your SoC

Both RISC and DSP functionality are needed to meet the expanding demands of edge...
Everything Low Power

What Does “Low Power Optimization” Mean To You?

Different power concerns lead to different solutions....
Power Source

Design For Silicon Success At 7nm

Rising complexity and tighter design margins increase the cost, and likelihood, ...
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?

Power integrity optimization can no longer be a reactive step in the backend pro...
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

Is 7nm The Last Major Node?

Technical issues increase, costs go up, and not all markets will benefit.

Machine Learning Meets IC Design

There are multiple layers in which machine learning can help with the creation of semiconductors, but getting there is not as simple as for other application areas.

The Darker Side Of Machine Learning

Machine learning needs techniques to prevent adversarial use, along with better data protection and management.

IoT Startups Rake In Cash

Funding is free-flowing for the field, but hurdles persist.

Transistor Aging Intensifies At 10/7nm And Below

Device degradation becomes limiting factor in IC scaling, and a significant challenge in advanced SoCs.