Low Power-High Performance

Top Stories

Test More Complex For Cars, IoT

Safety-critical markets add new challenges for testing methodology, which can affect functionality, reliability and yield.

New Memories And Architectures Ahead

So far there is not widespread adoption, but many see change as inevitable.

What Can Be Cut From A Design?

Doing more with less equates to bigger design challenges.

Routing Signals At 7nm

Teklatech's CEO talks about the challenges of scaling and how to minimize IR drop and timing issues.

Performance Increasingly Tied To I/O

Chipmakers look beyond processor speeds as rate of performance improvements slow.

Choosing Power-Saving Techniques

There are so many options that the best ones aren't always obvious.

Power State Switching Gets Tougher

Understanding and implementing power state switching delays can make or break a design.

Mobile Processors Move Beyond Phones

Qualcomm, other vendors look to autos, drones, and other applications.

2017: Manufacturing And Markets

Part 1: The future of Moore's Law, new architectures and packaging, and a spike in automotive, artificial intelligence and virtual/augmented realit...

Chip Advances Play Big Role In Cloud

Semiconductor improvements add up to big savings in power and performance.

More Top Stories »

Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »


Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Power Reduction

Why getting granular about energy can yield huge savings and how to utilize idle time.

Tech Talk: Lower Power Embedded NVM

How to increase the battery life in low power devices.

Tech Talk: Power Emulation

Using hardware-assisted verification to tackle complex power issues in SoC design.

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Latest Blogs

Editor's Note

Fix Processes, Then Silos

Adapting engineering organizations to deal with power and security is as complic...
Power Awareness

Adapting Formal

Formal technology has long been accepted as a powerful verification tool. It's m...
Power Source

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis

Getting the design right the first time has higher stakes than ever before....
IP And LP In SoCs

Advantages Of Designing With PCI Express 4.0 Draft 0.7 And PIPE 4.4 Specificatio

What's new in PCIe 4.0 and why to start developing designs now....
A Bit About Memory

The Challenges Of Designing An HBM2 PHY

As designers work to move higher bandwidth closer to the CPU, HBM is gaining mom...
At The Core

Real-Time Virtualization – How Hard Can It Be?

Virtualization can help meet safety goals in embedded systems....
Best Of Both: LP & HP

Finding The Unexpected In High Performance Designs

When something out of the ordinary happens, sometimes you want to go back and ha...
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....
Everything Low Power

Multiple Dimensions Of Low-Power Verification With Portable Stimulus

Even without a UPF file, having a portable stimulus model saves time and effort....
On-Chip Power Integrity

Dynamic Peak Power As A Proxy For DVD? Really?

Optimizing for dynamic voltage drop at the beginning of physical implementation....

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

What Are FeFETs?

How this new memory stacks up against existing non-volatile memory.

Battling Fab Cycle Times

Why it’s taking longer to manufacture chips at 10/7nm and what can be done about it.

New Memories And Architectures Ahead

So far there is not widespread adoption, but many see change as inevitable.

What’s New In Connected Autos

Internet of Things technology will be crucial to automobiles, but connectivity comes at a price.

Betting On Wafer-Level Fan-Outs

Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.