Low Power-High Performance

Top Stories

In-Chip Monitoring Becoming Essential Below 10nm
Complex interactions and power-related effects require understanding of how chips behave in context of real-world use cases.
Published on May 20th,  2019 by Ann Steffora Mutschler

The Growing Uncertainty Of Sign-Off At 7/5nm
Checking the electrical characteristics of circuits is becoming much more challenging.
Published on May 9th,  2019 by Ann Steffora Mutschler

The Limits Of Energy Harvesting
Why the promise of unlimited power in end devices has achieved only spotty success.
Published on May 9th,  2019 by Ed Sperling and Kevin Fogarty

Raising The Abstraction Level For Power
Finding the right abstraction for power analysis and optimization comes from tool integration.
Published on May 9th,  2019 by Brian Bailey

Designing For The Edge
Growth in data is fueling many more options, but so far it's not clear which of them will win.
Published on April 17th,  2019 by Ann Steffora Mutschler

Target: 50% Reduction In Memory Power
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
Published on April 11th,  2019 by Brian Bailey

Low Power Meets Variability At 7/5nm
Reductions in voltage, margin and increases in physical effects are making timing closure and signoff much more difficult.
Published on April 11th,  2019 by Ann Steffora Mutschler

Optimization Challenges For Safety And Security
The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.
Published on April 11th,  2019 by Brian Bailey

The Growing Challenge Of Thermal Guard-Banding
Margin is still necessary, but it needs to be applied more precisely than in the past.
Published on March 18th,  2019 by Ann Steffora Mutschler

Using Less Power At The Same Node
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.
Published on March 14th,  2019 by Brian Bailey

More Top Stories »



Round Tables

Planning For 5G And The Edge
Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.
Published on January 23rd,  2019 by Ed Sperling

Process Variation And Aging
Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.
Published on January 17th,  2019 by Ann Steffora Mutschler

Aging In Advanced Nodes
Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.
Published on September 17th,  2018 by Ann Steffora Mutschler

Process Variation Not A Solved Issue
Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.
Published on August 9th,  2018 by Ann Steffora Mutschler

Architecting For AI
Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?
Published on July 17th,  2018 by Ann Steffora Mutschler

More Roundtables »



Multimedia

Latency Under Load: HBM2 vs. GDDR6
Why choosing memory depends upon data traffic.
Published on May 9th,  2019 by Ed Sperling

New Challenges For Data Centers
Scalability and cost emerge as top issues with increased data volume.
Published on May 8th,  2019 by Ed Sperling

Multi-Physics At 5/3nm
Why process, voltage and temperature are so interrelated at future nodes, and what impact that has on design.
Published on April 11th,  2019 by Ed Sperling

GDDR6 – HBM2 Tradeoffs
What type of DRAM works best where.
Published on April 10th,  2019 by Ed Sperling

2.5D, 3D Power Integrity
Things to consider in advanced packaging.
Published on March 14th,  2019 by Ed Sperling

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Bottlenecks For Edge Processors
New processors will be blazing fast, but that doesn't guarantee improvements ...
May 9, 2019
by Ed Sperling
At The Core

Driving AI, ML To New Levels On MCUs
With the continued expansion of edge devices, new ways must be found to expan...
by Rhonda Dirvin
Best Of Both: LP & HP

ASIC/IC Trends With A Focus On Factors Of Silicon Success
Is increased verification effort paying off?
by Harry Foster
A Bit About Memory

Engineering The Signal For GDDR6
Advanced extraction tools and accurate models are key to a successful GDDR6 i...
by Shawn Nikoukary
IP And LP In SoCs

The Rising Importance Of Design Planning
The requirements of advanced process nodes call for a closer look at an often...
by Jim Schultz
Everything Low Power

IC Test: Doing It At The Right Place At The Right Time
Understand the different DFT technologies to know when to insert them into a ...
March 14, 2019
by Rohit Kapur
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding
What a difference a few degrees can make.
February 14, 2019
by Ramsay Allen
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea
The impact of coupling on designs and what to watch out for.
December 19, 2018
by Magdy Abadir
Power Awareness

Aging Analysis Hits Mainstream
Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
by Ann Steffora Mutschler
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package
Conflicting goals make arranging copper pillars or micro bumps around hard IP...
by Andy Heinig
Power Source

Getting Ahead With Early Power Analysis
Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018
by Annapoorna Krishnaswamy

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Limits Of Energy Harvesting

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Pre-characterized tiles can move Moore’s Law forward, but it’s not as easy as it looks.

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5G Heats Up Base Stations

Inefficient conversion of RF to digital and continuous connectivity issues are causing thermal problems, threatening signal integrity and reliability.

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Creating A Roadmap For Hardware Security

Government and private organizations developing blueprints for semiconductor industry as threat level rises.

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Challenges In Making And Testing STT-MRAM

Next-gen memory offers speed of SRAM and unlimited endurance, but it’s not a simple technology to work with.

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