Low Power-High Performance

Top Stories

In-Chip Monitoring Becoming Essential Below 10nm

Complex interactions and power-related effects require understanding of how chips behave in context of real-world use cases.

The Growing Uncertainty Of Sign-Off At 7/5nm

Checking the electrical characteristics of circuits is becoming much more challenging.

The Limits Of Energy Harvesting

Why the promise of unlimited power in end devices has achieved only spotty success.

Raising The Abstraction Level For Power

Finding the right abstraction for power analysis and optimization comes from tool integration.

Designing For The Edge

Growth in data is fueling many more options, but so far it's not clear which of them will win.

Target: 50% Reduction In Memory Power

Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.

Low Power Meets Variability At 7/5nm

Reductions in voltage, margin and increases in physical effects are making timing closure and signoff much more difficult.

Optimization Challenges For Safety And Security

The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.

The Growing Challenge Of Thermal Guard-Banding

Margin is still necessary, but it needs to be applied more precisely than in the past.

Using Less Power At The Same Node

When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.

More Top Stories »



Round Tables

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

More Roundtables »



Multimedia

Latency Under Load: HBM2 vs. GDDR6

Why choosing memory depends upon data traffic.

New Challenges For Data Centers

Scalability and cost emerge as top issues with increased data volume.

Multi-Physics At 5/3nm

Why process, voltage and temperature are so interrelated at future nodes, and what impact that has on design.

GDDR6 – HBM2 Tradeoffs

What type of DRAM works best where.

2.5D, 3D Power Integrity

Things to consider in advanced packaging.

More Multimedia »



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Latest Blogs

Editor's Note

Bottlenecks For Edge Processors

New processors will be blazing fast, but that doesn't guarantee improvements ...
May 9, 2019
At The Core

Driving AI, ML To New Levels On MCUs

With the continued expansion of edge devices, new ways must be found to expan...
Best Of Both: LP & HP

ASIC/IC Trends With A Focus On Factors Of Silicon Success

Is increased verification effort paying off?
A Bit About Memory

Engineering The Signal For GDDR6

Advanced extraction tools and accurate models are key to a successful GDDR6 i...
IP And LP In SoCs

The Rising Importance Of Design Planning

The requirements of advanced process nodes call for a closer look at an often...
Everything Low Power

IC Test: Doing It At The Right Place At The Right Time

Understand the different DFT technologies to know when to insert them into a ...
March 14, 2019
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding

What a difference a few degrees can make.
February 14, 2019
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.
December 19, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Limits Of Energy Harvesting

Why the promise of unlimited power in end devices has achieved only spotty success.

Chiplet Momentum Builds, Despite Tradeoffs

Pre-characterized tiles can move Moore’s Law forward, but it’s not as easy as it looks.

5G Heats Up Base Stations

Inefficient conversion of RF to digital and continuous connectivity issues are causing thermal problems, threatening signal integrity and reliability.

Creating A Roadmap For Hardware Security

Government and private organizations developing blueprints for semiconductor industry as threat level rises.

Challenges In Making And Testing STT-MRAM

Next-gen memory offers speed of SRAM and unlimited endurance, but it’s not a simple technology to work with.