Low Power-High Performance

Top Stories

How To Improve Analog Design Reuse

Existing design approaches remain inefficient, error-prone and highly customized, but that could change.

Design For Advanced Packaging

Stacking die is garnering more attention, but design flows aren’t fully ready to support it.

Taming NBTI To Improve Device Reliability

Negative-bias temperature instability can cause an array of problems at advanced nodes and reduced voltages.

Computing Way Outside Of A Box

Arm's CTO talks about how AI and the end of Moore's Law are shaking up processor design.

The Building Blocks Of Future Compute

How Arm sees its role in emerging segments of tomorrow’s compute challenges.

RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.

Power Issues Grow For Cloud Chips

Optimizing processor design in high-performance computing now requires lots of small changes.

Reliability, Machine Learning And Advanced Packaging

Experts at the Table, part 1: The biggest concerns in chip design and how new markets and technologies are affecting them.

Cloud Drives Changes In Network Chip Architectures

New data flow, higher switch density and IP integration create issues across the design flow.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

More Top Stories »

Round Tables

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

More Roundtables »


Hybrid Memory

Tech Talk: How long can DRAM scalIng continue?

Huge Performance Gains Ahead

Where the next boosts will come from and why.

UPF-Aware Clock-Domain Crossing

How to minimize the impact of CDC on power at RTL.

Aging Effects

How to model circuit degradation at advanced nodes.

In-Design Power Rail Analysis

What can go wrong with power analysis at advanced nodes.

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Latest Blogs

At The Core

Containing Design Complexity With POP IP

How to deal with complex power issues at advanced nodes.
November 16, 2018
A Bit About Memory

Die-to-Die Interconnects for Chip Disaggregation

How to speed up communication between dies in a package.
November 10, 2018
Editor's Note

Accelerators Everywhere. Now What?

An explosion in data will require a massive amount of hardware and software e...
November 8, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
Best Of Both: LP & HP

The Process Design Kit: Protecting Design Know-How

The key innovations that made pure-play foundries and the fabless revolution ...
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...
IP And LP In SoCs

Next-Generation Ethernet Interconnects For 400G Hyperscal...

The 400 Gb/s Ethernet standard provides a range of interfaces for varying len...
Everything Low Power

Psst, Says 5G… Wanna See What My New Antenna Tech C...

Power consumption remains a major barrier to 5G rollout.
Electromagnetic Crosstalk

Electromagnetic Analysis and Signoff: Cost Savings

How to improve reliability, trim manufacturing costs, and shorten time to mar...
September 18, 2018
Let's Talk PVT Monitoring

5 Reasons Why In-Chip Monitoring Is Here To Stay

From identifying hot spots to individualizing optimization schemes, it's impo...
September 13, 2018
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

The Impact of Moore’s Law Ending

Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.

Why Chips Die

Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.

AI Begins To Reshape Chip Design

Technology adds more granularity, but starting point for design shifts as architectures cope with greater volumes of data.

A Crisis In DoD’s Trusted Foundry Program?

GlobalFoundries’ decision to put 7nm on hold is raising concerns across the mil/aero industry.

Carmakers To Chipmakers: Where’s The Data?

Different perspectives and needs create friction as more advanced electronics are added into vehicles.