Low Power-High Performance

Top Stories

Taming Concurrency

What hoops will designers have to jump through to avoid concurrency bugs?

Mostly Upbeat Outlook For Chips

2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

Designing For Ultra-Low-Power IoT Devices

Battery-powered designs require complex optimizations for power in the context of area, performance and functionality.

What Makes A Chip Design Successful Today?

Maximum flexibility is no longer the reliable path to product success. While flexibility must be there for a purpose, it also can be a liability.

Impacts Of Reliability On Power And Performance

Determinism and coherency are becoming increasingly important as chips are used across a wide range of applications.

How To Improve Analog Design Reuse

Existing design approaches remain inefficient, error-prone and highly customized, but that could change.

Design For Advanced Packaging

Stacking die is garnering more attention, but design flows aren’t fully ready to support it.

Taming NBTI To Improve Device Reliability

Negative-bias temperature instability can cause an array of problems at advanced nodes and reduced voltages.

Computing Way Outside Of A Box

Arm's CTO talks about how AI and the end of Moore's Law are shaking up processor design.

More Top Stories »

Round Tables

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

More Roundtables »


Boosting Analog Reliability

Dealing with variability and physical effects in mixed signal designs.

Thermal Guard-Banding

Why more precision is necessary at advanced nodes.

Making Sense Of DRAM

What kind of memory is used where and why.

Hybrid Memory

Tech Talk: How long can DRAM scalIng continue?

Huge Performance Gains Ahead

Where the next boosts will come from and why.

More Multimedia »

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Latest Blogs

Editor's Note

Low Power At The Edge

What's the real impact of putting a supercomputer in your pocket?
January 17, 2019
IP And LP In SoCs

Efficient Hierarchical Verification For Low Power Designs

A new low power verification flow offers better runtime performance and reduc...
Best Of Both: LP & HP

Trends In FPGA Effectiveness: The 2018 Wilson Research Gr...

Last year, 84% of FPGAs went into production with non-trivial bug escapes.
At The Core

Cutting The Cord: How Edge Intelligence Is Enabling The I...

Adding more cloud compute won't solve the problem of managing exponentially g...
A Bit About Memory

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong

While PCIe 5.0 offers higher performance and lower latency, Gen 4 is likely s...
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.
December 19, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...
Everything Low Power

Psst, Says 5G… Wanna See What My New Antenna Tech C...

Power consumption remains a major barrier to 5G rollout.
Let's Talk PVT Monitoring

5 Reasons Why In-Chip Monitoring Is Here To Stay

From identifying hot spots to individualizing optimization schemes, it's impo...
September 13, 2018
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

What’s the Right Path For Scaling?

New architectures, packaging approaches gain ground as costs increase, but shrinking features continues to play a role.

The Next Semiconductor Revolution

Four industry experts talk about what’s changing, how quickly, and where the limits are with AI.

Quantum Issues And Progress

Work begins on building a quantum computing ecosystem.

Top Tech Talks Of 2018

Which videos had the most traffic and why.

More 2.5D/3D, Fan-Out Packages Ahead

Progress on 3D-ICs, using HBM with fan-outs, and other new approaches.