Low Power-High Performance

Top Stories

Power Impacting Cost Of Chips

The cost of designing a power delivery network is rising, and that's not likely to change.

The Ultimate Shift Left

Many implementation steps have been moving earlier in the design flow. Floorplanning is next, and it encompasses everything from architectural to p...

Worst-Case Results Causing Problems

At 10nm and 7nm, overdesign can affect power, performance and time to market.

Test More Complex For Cars, IoT

Safety-critical markets add new challenges for testing methodology, which can affect functionality, reliability and yield.

New Memories And Architectures Ahead

So far there is not widespread adoption, but many see change as inevitable.

What Can Be Cut From A Design?

Doing more with less equates to bigger design challenges.

Routing Signals At 7nm

Teklatech's CEO talks about the challenges of scaling, power integrity, and how to minimize IR drop and timing issues.

Performance Increasingly Tied To I/O

Chipmakers look beyond processor speeds as rate of performance improvements slow.

Choosing Power-Saving Techniques

There are so many options that the best ones aren't always obvious.

Power State Switching Gets Tougher

Understanding and implementing power state switching delays can make or break a design.

More Top Stories »

Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »


Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Power Reduction

Why getting granular about energy can yield huge savings and how to utilize idle time.

Tech Talk: Lower Power Embedded NVM

How to increase the battery life in low power devices.

Tech Talk: Power Emulation

Using hardware-assisted verification to tackle complex power issues in SoC design.

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Latest Blogs

Editor's Note

Power, Performance And Electronic Surveillance

Stopping governments from listening to your conversations at home will require m...
Power Awareness

Smart Antennas Come Into View

No longer invisible or unforgotten, antennas are getting smarter all the time. ...
A Bit About Memory

HBM2: It's All About The PHY

High-bandwidth memory is gaining significant traction, but poses unique challeng...
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?

Power integrity optimization can no longer be a reactive step in the backend pro...
IP And LP In SoCs

New USB Audio Class For USB Type-C Digital Headsets

How USB audio headsets can be power-competitive with analog and displace the 3.5...
Best Of Both: LP & HP

Correlating Software Execution With Switching Activity To Save Power In SoC Desi

A practical example of debugging a tricky power problem....
At The Core

Debug Is About To Get Really Interesting Again

Running trace and in-field debug through I/O is long overdue....
Power Source

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis

Getting the design right the first time has higher stakes than ever before....
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....
Everything Low Power

Multiple Dimensions Of Low-Power Verification With Portable Stimulus

Even without a UPF file, having a portable stimulus model saves time and effort....

Knowledge Centers
Entities, people and technologies explored

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