Low Power-High Performance

Top Stories

Cloud Computing Chips Changing

As cloud services adoption soars, datacenter chip requirements are evolving.

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budg...

The Problem With Clocks

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?

Managing Voltage Drop At 10/7nm

Building a power delivery network with the low implementation overhead becomes more problematic at advanced nodes.

Electric Vehicles Set The Pace

Developments in this part of the market will define low power and energy efficiency for years to come.

HBM Upstages DDR In Bandwidth, Power

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

Power Impacting Cost Of Chips

The cost of designing a power delivery network is rising, and that's not likely to change.

Antenna Design Grows Up

Modern electronics relies heavily on antennas, but companies still make mistakes. That's about to change.

The Ultimate Shift Left

Many implementation steps have been moving earlier in the design flow. Floorplanning is next, and it encompasses everything from architectural to p...

Worst-Case Results Causing Problems

At 10nm and 7nm, overdesign can affect power, performance and time to market.

More Top Stories »

Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »


Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Power Reduction

Why getting granular about energy can yield huge savings and how to utilize idle time.

Tech Talk: Lower Power Embedded NVM

How to increase the battery life in low power devices.

Tech Talk: Power Emulation

Using hardware-assisted verification to tackle complex power issues in SoC design.

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Latest Blogs

Editor's Note

The Hidden Costs Of Security

CEOs look at price tag and slow adoption. Impact on power and performance could ...
Power Awareness

Understanding Voltage Drop Mechanics

When it comes to understanding electricity, sometimes a down-to-earth explanatio...
Everything Low Power

The Efficiency Problem

Limitations for convolutional neural nets on DSP processors....
A Bit About Memory

Understanding SerDes Signal Integrity Challenges

Maintaining signal integrity is increasingly difficult as data rates move to 56G...
Power Source

Creating Reliable SoCs For Safe ADAS Applications

Automotive ICs need to be verified and validated in the context of the entire sy...
Best Of Both: LP & HP

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs

Handling design-specific power-aware verification complexities with SystemVerilo...
At The Core

Rethinking Computing For The AI Age

Moving AI out of the cloud requires a new approach to mobile architectures....
IP And LP In SoCs

Why You Need ASIL Certified Processor IP For Automotive Safety Applications

The long life cycle of automotive ICs means keeping future functional safety req...
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?

Power integrity optimization can no longer be a reactive step in the backend pro...
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

The Great Machine Learning Race

Chip industry repositions as technology begins to take shape; no clear winners yet.

HBM Upstages DDR In Bandwidth, Power

Design challenges and tool flow gaps emerge, but so do real-world PPA metrics.

22nm Process War Begins

High price of moving to finFETs pushes foundries to offer a less expensive alternative.

LiDAR Completes Sensing Triumvirate

Technology will complement cameras and radar in autonomous vehicles.

Moore’s Law: A Status Report

The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.