Low Power-High Performance

Top Stories

The Growing Challenge Of Thermal Guard-Banding

Margin is still necessary, but it needs to be applied more precisely than in the past.

Using Less Power At The Same Node

When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.

Memory Tradeoffs Intensify in AI, Automotive Applications

Why choosing memories and architecting them into systems is becoming much more difficult.

Using Analog For AI

Can mixed-signal architectures boost artificial intelligence performance using less power?

Gearing Up For 5G

This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.

Adapting Mobile To A Post-Moore’s Law Era

New techniques, architectures and approaches are making up for a reduction in scaling benefits.

Why Analog Designs Fail

Analog circuitry stopped following Moore’s Law a long time ago, but that hasn't always helped.

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

Power Issues Rising For New Applications

Why managing power is becoming more difficult, more critical, and much more expensive.

Taming Concurrency

What hoops will designers have to jump through to avoid concurrency bugs?

More Top Stories »



Round Tables

Planning For 5G And The Edge

Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.

Process Variation And Aging

Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.

Aging In Advanced Nodes

Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.

Process Variation Not A Solved Issue

Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

More Roundtables »



Multimedia

2.5D, 3D Power Integrity

Things to consider in advanced packaging.

Boosting Analog Reliability

Dealing with variability and physical effects in mixed signal designs.

Thermal Guard-Banding

Why more precision is necessary at advanced nodes.

Making Sense Of DRAM

What kind of memory is used where and why.

Hybrid Memory

Tech Talk: How long can DRAM scalIng continue?

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Power Budgets At 3nm And Beyond

Research is heating up at 3nm, and things are going to be very tight.
March 14, 2019
Everything Low Power

IC Test: Doing It At The Right Place At The Right Time

Understand the different DFT technologies to know when to insert them into a ...
Best Of Both: LP & HP

Trends In FPGA Verification Effort And Adoption: The 201...

FPGAs are growing more complex, but are verification techniques keeping up?
IP And LP In SoCs

The Importance Of Using The Right DDR SDRAM Memory

Unique architectural features tailor DRAM for specific applications.
A Bit About Memory

GDDR6: Signal Integrity Challenges For Automotive Systems

How PCB materials and vias can address insertion loss and crosstalk.
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding

What a difference a few degrees can make.
February 14, 2019
At The Core

Cutting The Cord: How Edge Intelligence Is Enabling The I...

Adding more cloud compute won't solve the problem of managing exponentially g...
January 17, 2019
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea

The impact of coupling on designs and what to watch out for.
December 19, 2018
Power Awareness

Aging Analysis Hits Mainstream

Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package

Conflicting goals make arranging copper pillars or micro bumps around hard IP...
Power Source

Getting Ahead With Early Power Analysis

Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018

Knowledge Centers
Entities, people and technologies explored


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Engineering Talent Shortage Now Top Risk Factor

New market opportunities and global competitiveness are limited by qualified people.

Finding Defects In Chips With Machine Learning

Better algorithms and more data could bolster adoption, particularly at advanced nodes.

The Challenge Of RISC-V Compliance

Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.

In-Memory Vs. Near-Memory Computing

New approaches are competing for attention as scaling benefits diminish.

Using Sensor Data To Improve Yield And Uptime

Deeper understanding of equipment behavior and market needs will have broad impact across the semiconductor supply chain.