Low Power-High Performance

Top Stories

The Growing Challenge Of Thermal Guard-Banding
Margin is still necessary, but it needs to be applied more precisely than in the past.
Published on March 18th,  2019 by Ann Steffora Mutschler

Using Less Power At The Same Node
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.
Published on March 14th,  2019 by Brian Bailey

Memory Tradeoffs Intensify in AI, Automotive Applications
Why choosing memories and architecting them into systems is becoming much more difficult.
Published on March 14th,  2019 by Ann Steffora Mutschler

Using Analog For AI
Can mixed-signal architectures boost artificial intelligence performance using less power?
Published on March 14th,  2019 by Brian Bailey

Gearing Up For 5G
This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.
Published on February 14th,  2019 by Brian Bailey

Adapting Mobile To A Post-Moore’s Law Era
New techniques, architectures and approaches are making up for a reduction in scaling benefits.
Published on February 14th,  2019 by Ann Steffora Mutschler

Why Analog Designs Fail
Analog circuitry stopped following Moore’s Law a long time ago, but that hasn't always helped.
Published on February 14th,  2019 by Brian Bailey

Planning For 5G And The Edge
Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.
Published on January 23rd,  2019 by Ed Sperling

Power Issues Rising For New Applications
Why managing power is becoming more difficult, more critical, and much more expensive.
Published on January 21st,  2019 by Ann Steffora Mutschler

Taming Concurrency
What hoops will designers have to jump through to avoid concurrency bugs?
Published on January 17th,  2019 by Brian Bailey

More Top Stories »



Round Tables

Planning For 5G And The Edge
Experts at the Table, part 2: Understanding 5G's benefits, limitations and design challenges.
Published on January 23rd,  2019 by Ed Sperling

Process Variation And Aging
Experts at the Table, part 2: How the very fast progress of the semiconductor industry is making transistor aging even more difficult.
Published on January 17th,  2019 by Ann Steffora Mutschler

Aging In Advanced Nodes
Experts at the Table, part 1: Why aging and reliability no longer can be addressed with margining in finFETs and automotive applications.
Published on September 17th,  2018 by Ann Steffora Mutschler

Process Variation Not A Solved Issue
Experts at the Table: Biggest issues with process variation today, and its impacts on the design process.
Published on August 9th,  2018 by Ann Steffora Mutschler

Architecting For AI
Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?
Published on July 17th,  2018 by Ann Steffora Mutschler

More Roundtables »



Multimedia

2.5D, 3D Power Integrity
Things to consider in advanced packaging.
Published on March 14th,  2019 by Ed Sperling

Boosting Analog Reliability
Dealing with variability and physical effects in mixed signal designs.
Published on January 17th,  2019 by Ed Sperling

Thermal Guard-Banding
Why more precision is necessary at advanced nodes.
Published on January 17th,  2019 by Ed Sperling

Making Sense Of DRAM
What kind of memory is used where and why.
Published on December 13th,  2018 by Ed Sperling

Hybrid Memory
Tech Talk: How long can DRAM scalIng continue?
Published on September 13th,  2018 by Ed Sperling

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

Editor's Note

Power Budgets At 3nm And Beyond
Research is heating up at 3nm, and things are going to be very tight.
March 14, 2019
by Ed Sperling
Everything Low Power

IC Test: Doing It At The Right Place At The Right Time
Understand the different DFT technologies to know when to insert them into a ...
by Rohit Kapur
Best Of Both: LP & HP

Trends In FPGA Verification Effort And Adoption: The 201...
FPGAs are growing more complex, but are verification techniques keeping up?
by Harry Foster
IP And LP In SoCs

The Importance Of Using The Right DDR SDRAM Memory
Unique architectural features tailor DRAM for specific applications.
by Vadhiraj Sankaranarayanan
A Bit About Memory

GDDR6: Signal Integrity Challenges For Automotive Systems
How PCB materials and vias can address insertion loss and crosstalk.
by Frank Ferro
Let's Talk PVT Monitoring

How To Reduce Thermal Guard-Banding
What a difference a few degrees can make.
February 14, 2019
by Ramsay Allen
At The Core

Cutting The Cord: How Edge Intelligence Is Enabling The I...
Adding more cloud compute won't solve the problem of managing exponentially g...
January 17, 2019
by Chris Shore
Electromagnetic Crosstalk

How to Make Sure IP will Float in the Rough SoC Sea
The impact of coupling on designs and what to watch out for.
December 19, 2018
by Magdy Abadir
Power Awareness

Aging Analysis Hits Mainstream
Increasingly, the ability to address transistor aging is showing up in EDA to...
November 8, 2018
by Ann Steffora Mutschler
Spotlight On Reliability

Interaction Of Hard IP And Chip-Package
Conflicting goals make arranging copper pillars or micro bumps around hard IP...
by Andy Heinig
Power Source

Getting Ahead With Early Power Analysis
Increased power density is causing mounting power and thermal concerns that n...
August 9, 2018
by Annapoorna Krishnaswamy

Knowledge Centers
Entities, people and technologies explored


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Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.

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New approaches are competing for attention as scaling benefits diminish.

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Using Sensor Data To Improve Yield And Uptime

Deeper understanding of equipment behavior and market needs will have broad impact across the semiconductor supply chain.

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