Low Power-High Performance

Top Stories

Modeling On-Chip Variation At 10/7nm

Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required.

Transient Power Problems Rising

At 10/7nm, power management becomes much more difficult; old tricks don't work.

Hardware/Software Tipping Point

Has the tide turned from increasing amounts of general purpose, software defined products, to one where custom hardware will make a comeback?

Maintaining Power Profiles At 10/7nm

Capturing what is driving power in a design means different things to different teams, but it's essential at 10nm and below.

Power Challenges At 10nm And Below

Dynamic power density and rising leakage power becoming more problematic at each new node.

Closing The Loop On Power Optimization

Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to ac...

Analog’s Unfair Disadvantage

In a world that favors digital circuitry, analog has increasingly had to cope with processes that have become less favorable to them. But that may ...

Cloud Computing Chips Changing

As cloud services adoption soars, datacenter chip requirements are evolving.

The Hunt For A Low-Power PHY

The physical layer interface is necessary for a chip to access the outside world, but it threatens to consume increasing portions of the power budg...

The Problem With Clocks

Clocks are power- and area- hungry, and difficult to distribute in a controlled manner. What is being done to reign in these unwieldy beasts?

More Top Stories »

Round Tables

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 3: Modeling accuracy, skin effects and new packaging techniques take center stage.

The Future Of Memory

Experts at the table, part 3: Security, process variation, shortage of other IP at advanced nodes, and too many foundry processes.

Optimization Challenges For 10nm And 7nm

Experts at the Table, Part 2: Heat is becoming a serious issue as thermal densities rise and this creates problems for industries such as automotiv...

Optimization Challenges For 10nm And 7nm

Experts at the Table, part 1: What will it take to optimize a design at 10nm and 7nm? The problem gets harder with each new node.

Mixed-signal/Low-power Design

Experts at the table, part 3: EDA vendors respond to the challenges posed by the chip companies.

More Roundtables »


Tech Talk: 7nm Power

Dealing with thermal effects, electromigration and other issues at the most advanced nodes.

Tech Talk: Neural Networks

How to design and implement convolution neural networks, and what to watch out for.

Tech Talk: Power Signoff

A look at the impact of margin in advanced designs and how to ensure there is sufficient coverage.

Tech Talk: Micro-Architecting Power

A deep dive into how to save power by leveraging idle time.

Tech Talk: Power Reduction

Why getting granular about energy can yield huge savings and how to utilize idle time.

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Latest Blogs

Editor's Note

Age Of Acceleration

Focus shifts from the fastest processors to faster processes. ...
Power Awareness

ESD Guns, Transients And Testing…Oh My!

Sometimes a shock to the system is a good thing....
A Bit About Memory

From SerDes Chiplets To Die-To-Die Interfaces

As demand for higher bandwidth within a similar power envelope grows, so does th...
Everything Low Power

What Does “Low Power Optimization” Mean To You?

Different power concerns lead to different solutions....
IP And LP In SoCs

The Evolution Of Deep Learning For ADAS Applications

Advances in embedded vision are powering autonomous driving....
At The Core

Large-Screen Compute Transformation Is Here

A new chapter is beginning for mobile devices....
Best Of Both: LP & HP

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation

Understanding the Liberty syntax and other non-standard behavioral model librari...
Power Source

Design For Silicon Success At 7nm

Rising complexity and tighter design margins increase the cost, and likelihood, ...
On-Chip Power Integrity

10nm And 7nm Routability - How Is Your CAD Flow Doing?

Power integrity optimization can no longer be a reactive step in the backend pro...
Power Architect

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon....

Knowledge Centers
Entities, people and technologies explored

  Trending Articles

RISC-V Pros And Cons

Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

Samsung Unveils Scaling, Packaging Roadmaps

Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.

Shrink Or Package?

Advanced packaging shifts to mainstream with complete flows, better tools, market proof points.

The LiDAR Gold Rush

LiDAR firms attract investments as corporate and venture investors vie for a piece of this burgeoning market.

What’s Next In Scaling, Stacking

The 40nm gate-pitch cliff, 3D SoCs with microfluidic cooling, new fan-outs and 2.5D—it’s all on the table.