Low Power-High Performance

Top Stories

5nm Design Progress

Improvements in power, performance and area are much more difficult to achieve, but solutions are coming into focus.

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Five DAC Keynotes

Thought-provoking talks about the future of technology, how to improve it, and what it means for design engineers.

Defining Edge Memory Requirements

Edge compute covers a wide range of applications. Understanding bandwidth and capacity needs is critical.

IoT Wireless Battles Ahead

Tradeoffs include power, performance, security. Each standard has its own benefits and drawbacks.

Chip Dis-Integration

Continued integration is no longer the natural way forward for semiconductors. What needs to happen to make it easier?

Near-Threshold Issues Deepen

Process variation plus timing are adding to low-power challenges at the most advanced nodes.

Complexity, Reliability And Cost

Fraunhofer EAS's top scientist digs into new technical and business challenges shaping the semiconductor industry.

Ensuring Chip Reliability From The Inside

In-chip monitoring techniques are growing for automotive, industrial, and data center applications.

Analog Migration Equals Redesign

Advanced nodes are forcing design teams to make tradeoffs at each new node and with each new process.

More Top Stories »



Round Tables

Architecting For AI

Experts at the Table, part 1: What kind of processing is required for inferencing, what is the best architecture, and can they be debugged?

Power Modeling And Analysis

Experts at the Table, part 3: Juggling accuracy and fidelity while making the problem solvable with finite compute resources and exciting developme...

Power Modeling and Analysis

Experts at the Table, part 2: What does a power model look like and how do you ensure software utilizes power control properly?

Power Modeling And Analysis

Experts at the Table, part 1: Are power models created early enough to be useful, and is that the best approach?

IP Challenges Ahead

Part 2: For the IP industry to remain healthy it has to constantly innovate, but it's getting harder.

More Roundtables »



Multimedia

Aging Effects

How to model circuit degradation at advanced nodes.

In-Design Power Rail Analysis

What can go wrong with power analysis at advanced nodes.

Tech Talk: Data-Driven Design

How more data is shifting memory architectures.

Tech Talk: HBM vs. GDDR6

A look at two different memory options, and the pros and cons of each.

Tech Talk: Shrink Vs. Package

Tradeoffs between putting everything onto a single chip and different advanced packaging options.

More Multimedia »



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Latest Blogs

Editor's Note

Energy At The Edge

How much energy will billions of complex devices require?
July 17, 2018
Best Of Both: LP & HP

Power-Aware Static Checks: Static Checker Results And Deb...

Understand what PA-Static reports are telling you for efficient debugging.
Let's Talk PVT Monitoring

Explaining Adaptive Voltage Scaling And Dynamic Voltage F...

Voltage monitoring enables two techniques for optimizing in-chip conditions.
IP And LP In SoCs

Enabling Integrated ADAS Domain Controllers With Automoti...

Meeting safety requirements for changing automotive SoC architectures.
At The Core

Five Features Of The ‘Always-On’ Mobile Exper...

What capabilities are consumers expecting in the next generation of mobile de...
Everything Low Power

Can Machine Learning Chips Help Develop Better Tools With...

New AI chips require an extreme level of architectural complexity, making rou...
June 18, 2018
Electromagnetic Crosstalk

Is It Time To Take Inductance And Electromagnetic Effects...

Experts disagree about the impact of crosstalk on today's large mixed-signal ...
June 14, 2018
Power Source

Beyond Signoff

To deal with increased variability at advanced nodes, new methodologies are n...
Spotlight On Reliability

Upcoming System Modeling Challenges

Why it's important to incorporate reliability information into the concept ph...
A Bit About Memory

5G Wireless Infrastructure Pushes High-Speed SerDes Proto...

Reducing SerDes latency variation and jitter is necessary for long-reach netw...
Power Awareness

Heterogeneous Hubbub

The combination of heterogenous architectures and RISC-V is encouraging new t...
March 8, 2018

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Big Trouble At 3nm

Costs of developing a complex chip could run as high as $1.5B, while power/performance benefits are likely to decrease.

Quantum Computing Becoming Real

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Security Holes In Machine Learning And AI

A primary goal of machine learning is to use machines to train other machines. But what happens if there’s malware or other flaws in the training data?

Bridges Vs. Interposers

Momentum growing for low-cost alternatives to interposers as a way of reducing overall development costs.

The Darker Side Of Consolidation

What happens when companies are combined? The outcome often isn’t as good as the announcement.