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What Designers Need to Know About Error Correction Code (ECC) In DDR Memories


As with any electronic system, errors in the memory subsystem are possible due to design failures/defects or electrical noise in any one of the components. These errors are classified as either hard-errors (caused by design failures) or soft-errors (caused by system noise or memory array bit flips due to alpha particles, etc.). To handle these memory errors during runtime, the memory subsyst... » read more

Essential DDR5 Features Designers Must Know


JEDEC has defined and developed three DDR standards – standard DDR, mobile DDR, and graphic DDR – to help designers meet their memory requirements. DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article... » read more

The Importance Of Using The Right DDR SDRAM Memory


Selecting the right memory technology is often the most critical decision for achieving the optimal system performance. Designers continue to add more cores and functionality to their SoCs; however, increasing performance while keeping power consumption low and silicon footprint small remains a vital goal. DDR SDRAMs, DRAMs in short, meet these memory requirements by offering a dense, high-perf... » read more