Aparna Tarde

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Aparna Tarde is a Senior Staff Technical Product Manager responsible for the die-to-die interface IP product line at Synopsys. She previously worked as a design engineer at Intel designing cloud-based accelerator systems using PCIe, Ethernet, and DDR. Tarde has held different positions from design verification to applications engineering and has extensive knowledge in system design using FPGAs in data centers. She holds a master’s degree in electrical engineering from San Jose State University.

Author's Latest Posts

Why 40G UCIe IP?

By Aparna Tarde - 31 Oct, 2024 - Comments: 0

AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more