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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Challenges With Adaptive Control
By Brian Bailey - 08 Dec, 2022 - Comments: 0

Historically, the performance and power consumption of a system was controlled by what could be done at design time, but chips today are becoming a lot more adaptive. This has become a necessity for cutting edge nodes, but also provides a lot of additional benefits at the expense of greater complexity and verification challenges. Design margins are a tradeoff between performance and yield. C... » read more

Is UCIe Really Universal?
By Brian Bailey - 22 Nov, 2022 - Comments: 3

Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

The Politics Of Standards
By Brian Bailey - 22 Nov, 2022 - Comments: 1

Standards often are seen as an industry coming together to agree upon a common solution to a common problem, but there are times when this could not be further from the truth. Having been involved in standards at all levels — from participant to chair for several standards — some were successful, some were not, some are seeing significant adoption while others are withering by the wayside, ... » read more

The Drive Toward Virtual Prototypes
By Brian Bailey - 22 Nov, 2022 - Comments: 1

Chipmakers are piling an increasing set of demands on virtual prototypes that go well beyond its original scope, forcing EDA companies to significantly rethink models, abstractions, interfaces, view orthogonality, and flows. The virtual prototype has been around for at least 20 years, but its role has been limited. It has largely been used as an integration and analysis platform for models t... » read more

Taking Power Much More Seriously
By Brian Bailey - 10 Nov, 2022 - Comments: 0

An increasing number of electronic systems are becoming limited by thermal issues, and the only way to solve them is by elevating energy consumption to a primary design concern rather than a last-minute optimization technique. The optimization of any system involves a complex balance of static and dynamic techniques. The goal is to achieve maximum functionality and performance in the smalles... » read more

A Power-First Approach
By Brian Bailey - 27 Oct, 2022 - Comments: 7

It is becoming evidently clear that heat will be the limiter for the future of semiconductors. Already, large percentages of a chip are dark at any time, because if everything operated at the same time the amount of heat generated would exceed the ability of the chip and package to dissipate that energy. If we now start to contemplate stacking dies, where the ability to extract heat remains con... » read more

Raising IP Integration Up A Level
By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Bug-Free Designs
By Brian Bailey - 27 Oct, 2022 - Comments: 0

It is possible in theory to create a design with no bugs, but it's impractical, unnecessary, and extremely difficult to prove for bugs you care about. The problem is intractable because the potential state space is enormous for any practical design. The industry has devised ways to handle this complexity, but each has limitations, makes assumptions, and employs techniques that abstract the p... » read more

Foundational Changes In Chip Architectures
By Brian Bailey - 13 Oct, 2022 - Comments: 5

We take many things in the semiconductor world for granted, but what if some of the decisions made decades ago are no longer viable or optimal? We saw a small example with finFETs, where the planar transistor would no longer scale. Today we are facing several bigger disruptions that will have much larger ripple effects. Technology often progresses in a linear fashion. Each step provides incr... » read more

Verification Methodologies Evolve, But Slowly
By Brian Bailey - 29 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

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