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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

How To Optimize A Processor
By Brian Bailey - 26 May, 2022 - Comments: 0

Optimizing any system is a multi-layered problem, but when it involves a processor there are at least three levels to consider. Architects must be capable of thinking across these boundaries because the role of each of the layers must be both understood and balanced. The first level of potential optimization is at the system level. For example, how does data come in and out of the processing... » read more

Is AI Improving A Broken Process?
By Brian Bailey - 26 May, 2022 - Comments: 0

Verification is fundamentally comparing two models, each derived independently, to find out if there are any different behaviors expressed between the two models. One of those models represents the intended design, and the other is part of the testbench. In an ideal flow, the design model would be derived from the specification, and each stage of the design process would be adding other deta... » read more

The Challenge Of Optimizing Chip Architectures For Workloads
By Brian Bailey - 12 May, 2022 - Comments: 1

It isn't possible to optimize a workload running on a system just by looking at hardware or software separately. They need to be developed together and intricately intertwined, an engineering feat that also requires bridging two worlds with have a long history of operating independently. In the early days of computing, hardware and software were designed and built by completely separate team... » read more

The Industrial Revolution Is Over
By Brian Bailey - 28 Apr, 2022 - Comments: 0

One of the greatest impacts of the industrial revolution was that better communication allowed for greater specialization, and with that came better economics. There have been multiple waves of the industrial revolution, each triggered by some improvement in communications. The first wave was all about trains — raw materials and finished goods could be quickly and cheaply moved between cit... » read more

Choosing Which Tasks To Optimize In Chips
By Brian Bailey - 28 Apr, 2022 - Comments: 0

The optimization of one or more tasks is an important aspect of every SoC created, but with so many options now on the table it is often unclear which is best. Just a few years ago, most people were happy to buy processors from the likes of Intel, AMD and Nvidia, and IP cores from Arm. Some even wanted the extensibility that came from IP cores like Tensilica and ARC. Then, in 2018, John Henn... » read more

The Challenges Of Incremental Verification
By Brian Bailey - 28 Apr, 2022 - Comments: 1

Verification consumes more time and resources than design, and yet little headway is being made to optimize it. The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences? ... » read more

Architecting Faster Computers
By Brian Bailey - 14 Apr, 2022 - Comments: 3

To create faster computers, the industry must take a major step back and re-examine choices that were made half a century ago. One of the most likely approaches involves dropping demands for determinism, and this is being attempted in several different forms. Since the establishment of the von Neumann architecture for computers, small, incremental improvements have been made to architectures... » read more

Clocks Getting Skewed Up
By Brian Bailey - 30 Mar, 2022 - Comments: 0

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it's fraught with the most problems at the physical level. To some, the clock is the AC power supply of the chip. To others, it is an analog network almost beyond analysis. Ironically, there are no languages to describe clocking, few tools t... » read more

UCIe: Marketing Ruins It Again
By Brian Bailey - 24 Mar, 2022 - Comments: 1

You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

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