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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Education Vs. Training
By Brian Bailey - 26 Aug, 2021 - Comments: 1

While writing my recent articles on the subject of training, a number of people pointed out that training and education are not the same thing. In a very simple sense, training is defined to be learning a skill or behavior that enables you to 'do' something, whereas education is the acquisition of knowledge from study or training. These definitions leave me cold and, in my mind, miss a very ... » read more

Steering The Semiconductor Industry
By Brian Bailey - 26 Aug, 2021 - Comments: 2

Progress in semiconductors has been one of the most successful engineering feats, and the industry has ridden an exponential curve longer than anything else in history. It is also a highly conservative industry that has pushed away many disruptive changes in favor of small incremental changes that minimize risk. There have been significant changes over the decades, and they often required a ... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Adding Circuit Aging To Variability
By Brian Bailey - 12 Aug, 2021 - Comments: 0

Moving to a smaller node usually means another factor becomes important. The industry has become accustomed to doing process, temperature, voltage (PVT) corner analysis, but now it has to add aging into that mix. The problem is that planning for circuit aging is no longer a purely statistical process. Aging is dependent on activity over the lifetime of the device. Tools need to be modified a... » read more

Rethink, Not Replicate
By Brian Bailey - 29 Jul, 2021 - Comments: 0

We should start to call COVID the Great Disrupter. It caused many things to change, ranging from how the industry has been tackling education, to supply chains, the ability to find products in stores, and the pricing and availability of materials, workers, and office space. I can't see anyone fully trusting just-in-time supply chains anymore, even though they sometimes provided financial advant... » read more

Challenges For New AI Processor Architectures
By Brian Bailey - 29 Jul, 2021 - Comments: 0

Investment money is flooding into the development of new AI processors for the data center, but the problems here are unique, the results are unpredictable, and the competition has deep pockets and very sticky products. The biggest issue may be insufficient data about the end market. When designing a new AI processor, every design team has to answer one fundamental question — how much flex... » read more

Continuous Education For Engineers
By Brian Bailey - 29 Jul, 2021 - Comments: 0

Continuous education is essential for engineers, but many companies don't recognize the value or they are unwilling to provide the necessary resources. This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but also impacts the value they can provide to that company during the course of the... » read more

Chipmakers Getting Serious About Integrated Photonics
By Brian Bailey - 12 Jul, 2021 - Comments: 3

Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

Reducing Power Delivery Overhead
By Brian Bailey - 08 Jul, 2021 - Comments: 0

The power delivery network (PDN) is a necessary overhead that typically remains in the background — until it fails. For chip design teams, the big question is how close to the edge are they willing to push it? Or put differently, is the gain worth the pain? This question is being scrutinized in very small geometry designs, where margins can make a significant difference in device performan... » read more

Debug: The Schedule Killer
By Brian Bailey - 30 Jun, 2021 - Comments: 0

Debug often has been labeled the curse of management and schedules. It is considered unpredictable and often can happen close to the end of the development cycle, or even after – leading to frantic attempts at work-arounds. And the problem is growing. "Historically, about 40% of time is spent in debug, and that aspect is becoming more complex," says Vijay Chobisa, director of product manag... » read more

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