Author's Latest Posts


AI Effort And Money Misplaced


While it is early days, and innovation is important, hyperscalers cannot afford to keep throwing money away forever. They need to work out how AI will earn money, and that relies on inference. For some time, I have been intrigued by the amount of money being spent on model development and AI training compared to the investment in inference. Models are an enabler, and every new model is attem... » read more

Verification Fails To Keep Up


Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Re-Architecting AI For Power


The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

Hallucination And Innovation At DAC


At DAC this year, I had the pleasure of moderating an intimate chat between Alon Shtepel, senior director for ASIC at Micron, and Abhi Kolpekwar, vice president and general manager for digital verification technology at Siemens EDA. The assigned topic was generative AI in design and verification, with the more provocative subtitle asking if we are hallucinating or innovating? L-R: Brian ... » read more

Multi-Modal AI In EDA Development Flows


RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

When Standards Enable Chiplets


Semiconductor Engineering sat down and discussed the need for standards to enable an ecosystem for chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kr... » read more

Chiplet Ecosystem Slowly Emerges


Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

When Can I Buy A Chiplet?


One year ago, Semiconductor Engineering conducted its first roundtable to find out the true state of the industry for chiplets. At that event, it was stated that no chiplet had ever been reused in a design for which it was not initially intended. How much has changed over the past year? Returning from last year were Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice... » read more

Iteration And Hallucination


Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal


Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

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