Author's Latest Posts


Noise: A Chip Killer


Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Formal Verification’s Value Grows


Experts at the table: Semiconductor Engineering sat down to discuss why formal verification is becoming more important, with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA. Wha... » read more

The Next Big Thing


Sometimes, we spend so much time looking for the next big thing that we actually miss something even bigger. I have to admit I was guilty of this while employed by a large EDA company 20 years ago. I was one of those ESL people — Electronic System Level acolytes, with Gary Smith as our standard bearer. We wanted to do many things, including raising the level of abstraction for design and veri... » read more

Advances In Formal Verification Technology


Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Current Problems Grow For Power Delivery


IR drop is becoming more problematic for a growing proportion of designs, an indication that the power delivery network (PDN) is not providing enough current to parts of the design when required. Unfortunately, there is no easy fix to this problem. In the past, when voltages were much higher, a small voltage droop didn't really matter. At the same time, wires were much thicker and presented ... » read more

What Does Semiconductor Disruption Look Like?


When conducting interviews for my article on the incorporation of AI within EDA tools, Anand Thiruvengadam, senior director and head of AI product management at Synopsys, said, "AI has the potential to transform how customers do chip design. The entire EDA flow can be disrupted with AI." He is not alone in making this kind of statement. Each year, I do a predictions piece, and I ask about how A... » read more

The Limits Of AI’s Role In EDA Tools


The world has been inspired by generative AI models like ChatGPT. These are very applicable to things like copilots and agentic AI, but the adoption of these models into EDA tools is less obvious. What may be appropriate, and can AI make EDA tools faster or better? EDA has been enabling Moore's Law for the past 40 years, and that has required pushing the limits of many of the algorithms and ... » read more

The Future Of Verification


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

New Demands For IP Reuse


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight;... » read more

The Demise Of Static Timing Verification?


The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

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