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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Minimum Energy Per Query
By Brian Bailey - 12 Feb, 2026 - Comments: 1

Key Takeaways Extracting heat from a chip faster is a short-term fix to a bigger problem. The longer-term challenge is how to reduce the amount of energy used per query. Data movement, guardbanding, and software inefficiency are key targets for the future. Heat is a serious problem within AI chips, and it is limiting how much processing can be done. The solution is either to... » read more

The Verification Conundrum
By Brian Bailey - 02 Feb, 2026 - Comments: 2

When constrained random test pattern generation became the de facto way to verify designs, reference models became necessary to check that a design was producing the correct output. These were often distributed across several models, such as checkers, scoreboards and assertions. Another model that had to be created was the coverage model. It was required because you had to know if a generate... » read more

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

Will 2026 Be Dominated By AI?
By Brian Bailey - 15 Jan, 2026 - Comments: 0

Many opportunities and problems became highly interlinked in 2025, fueled by the historic growth in everything AI. But how close are we coming to breaking points, and what are people doing to mitigate them? That is the story that will unfold this year. AI's penetration into an increasing number of workloads is placing almost quadratic demands on compute, memory, interconnect, and the archite... » read more

2025 – A Year Of Change And Anticipation
By Brian Bailey - 23 Dec, 2025 - Comments: 0

2025 has certainly been a year of unexpected changes. These had a significant impact on the semiconductor industry and everything that supports it. Not all the changes have been bad, but flexibility has been a requirement for continued success or to make the most of an opportunity provided. Some industries, such as aerospace and defense, are seeing a significant boost around the world. Data ... » read more

Tracking Your Preferences
By Brian Bailey - 23 Dec, 2025 - Comments: 0

I like to use my last blog of the year to focus on you, the reader. You provide valuable feedback to me and the rest of the team at Semiconductor Engineering. What do you want to see us write about? How in-depth should things be? This is always a balance between the amount of information provided and the rate at which readers tire with an article. My focus is the channels I write for – Sys... » read more

Limited by Power
By Brian Bailey - 11 Dec, 2025 - Comments: 0

AI is seen as a massive computation problem, but that is not the case, at least with the way that the problem is structured today. It is a data movement problem. This not only limits performance but represents most of the energy consumption. In addition, the industry spends most of its time and effort making small improvements that optimize aspects of the existing architecture, when what is ... » read more

AI Plays Multiple Roles Within EDA
By Brian Bailey - 25 Nov, 2025 - Comments: 0

AI's infusion into our world may seem sudden and unexpected, but EDA has been quietly adopting it for more than a decade. What's changed is that it's now becoming more visible, thanks to increasingly powerful large language models (LLMs) and the need to apply them to increasingly challenging multi-physics problems. Two fundamental shifts underlie AI's increasing prominence. First, heat is be... » read more

Spray And Pray Wastes Power
By Brian Bailey - 24 Nov, 2025 - Comments: 0

For quite some time I have felt that the way the industry approaches power is less than optimal. Techniques such as clock gating and power gating have been used to reduce the amount of unnecessary activity and leakage, but is there more activity that does not contribute to an intended action? While unnecessary activity may be unimportant in the functional sense, it all represents power that ... » read more

The Future For Formal Verification
By Brian Bailey - 19 Nov, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss possible future directions for formal verification technology with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemen... » read more

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