Joseph Hupcey III

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Joe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens, Hupcey has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, he worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.

Author's Latest Posts

Formal Verification Ensures The Perseverance Rover Lands Safely On Mars
By Joseph Hupcey III - 28 Apr, 2022 - Comments: 0

By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?
By Joseph Hupcey III - 03 Feb, 2022 - Comments: 0

Given the relative novelty and complexity of RISC-V RTL designs, whether you are buying a commercially supported core or downloading a popular open-source offering, there is the small but non-zero risk of unwanted surprises escaping undetected into your end-product. In order of high-to-low probability, consider: The presence of a weird-yet-entirely-possible corner-case bug Bugs “insid... » read more

When Things Go Wrong Even When You’re Doing the Right Thing
By Joseph Hupcey III - 28 May, 2015 - Comments: 0

By Kurt Takara and Joe Hupcey III “Isolation. Retention. Level shifters. Dynamic voltage scaling. I’m doing all the right things to reduce the power consumption of my design by adding all of this power control logic. But because of this new low power circuitry, I’m seeing fresh clock domain crossing (CDC) problems that are making my design do all the wrong things; and my trusty old low... » read more

User Case Study
By Joseph Hupcey III - 06 Nov, 2014 - Comments: 0

Whenever more than one clock is employed in an SoC (which is all SoCs), the risk of errors from clock domain crossings (CDC) – signals (or groups of signals) that are generated in one clock domain and consumed in another – is incredibly high. Unfortunately, CDC bugs are nearly impossible to catch with conventional simulations. Thus, all too often they escape into silicon. Debugging them in ... » read more

User Case Study: Using Formal To Verify Low Power Functionality And Eliminate Unwanted ‘Xs’
By Joseph Hupcey III - 10 Apr, 2014 - Comments: 3

The cynics among us might argue that the addition of low power circuitry is a clever scheme by the energy industry to cause an equal amount of power to be consumed by low power verification as is saved by end-user usage.  As if modern SoC verification wasn’t challenging enough, the addition of low power can create corner cases that can escape even the most well-written UVM testbenches.  Ind... » read more

Formally Verifying Security Aspects Of SoC Designs
By Joseph Hupcey III - 13 Mar, 2014 - Comments: 0

[youtube vid=e4SdOY3HUtU] » read more

The Other Side Of Formal
By Joseph Hupcey III - 13 Feb, 2014 - Comments: 1

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

User Case Study
By Joseph Hupcey III - 08 Nov, 2013 - Comments: 0

In prior articles I’ve written in general terms of about formally verifying the impact of adding low power control circuitry with Jasper’s Low Power Verification App. At the recent Jasper User’s Group meeting on Oct. 22, a real world case study of this app in action at STMicro’s R&D center in India was presented. Here are some highlights from this paper: DUT in question: an AR... » read more

How Secure Is Your Design?
By Joseph Hupcey III - 10 Oct, 2013 - Comments: 0

Once upon a time, secure hardware was only needed for mil-aero and banking systems. Today, numerous industrial and consumer applications require special hardware to protect data required for digital rights management, electronic wallets, private encryption keys, or medical information. Current methodologies to verify that such hardware is impervious to attack and/or the data within remains s... » read more

Equivalence Checking
By Joseph Hupcey III - 12 Sep, 2013 - Comments: 0

Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is required by the data center, etc. Clock-gating is one widely used technique to save power in ASIC designs. However, clock gating can significantly impact the structural and behavioral elements of the... » read more

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