Lee Moore

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Lee Moore is the lead engineer at Imperas for RISC-V processor models and simulation tools. Prior to Imperas, Moore worked as a senior consulting engineer for EDA vendors such as Co-Design Automation and Ambit, and for ASIC vendor NEC Electronics. Moore is also a private pilot, and recently developed PilotAware, a low-cost air traffic awareness device, helping aircraft to see and be seen.

Author's Latest Posts

RISC-V Verification: The 5 Levels Of Simulation-Based Processor Hardware DV

By Lee Moore - 29 Jul, 2021 - Comments: 1

By Lee Moore and Simon Davidmann The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating... » read more

Adding Value To Open-Source RISC-V Cores With Verification

By Lee Moore - 22 Apr, 2021 - Comments: 0

By Steve Richmond (Silicon Labs), Mike Thompson (OpenHW Group), and Lee Moore (Imperas Software) Modern SoC verification has matured to the point that some are suggesting the use of the word ‘prototype’ when referring to the first silicon samples is now unnecessary. This is due in part to the commercial EDA industry, which has provided the innovation and tools used throughout the design... » read more