Author's Latest Posts


An Automated Method For Adding Resiliency To Mission-Critical SoC Designs


Adding safety measures to system-on-chip (SoC) designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the Aerospace and Defense (A&D), cloud, automotive, robotics, medical, and Internet-of-Things (IoT) industries more resilient against random hardware failures that occur. Designing for reliable and resilient functionality doe... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies


An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

Accelerating Development of Software Defined Vehicles with Virtual ECUs


The automotive industry is going through a revolution. To adapt to new customer demands such as convenience, safety, autonomy, and electrification, the automotive industry is moving to software-driven vehicles. These require new, more powerful electrical/electronic (E/E) architectures and significantly increase the vehicle software content. They also force the industry to move from lengthy deve... » read more

Computational Imaging Craves System-Level Design And Simulation Tools To Leverage Disruptive AI In Embedded Vision


Image quality now relies more than ever on high computing power tied to miniaturized optics and sensors, rather than on standalone and bulky but aberration-free optics. This new trend is called computational imaging and can be used either for computational photography or for computer vision. Read this white paper to learn about market trends and promising system co-design and co-optimization ap... » read more

Achieving Consistent RTL Power Accuracy


Are you struggling to accurately estimate RTL power consumption early in your design process? RTL power estimation can be inaccurate due to the complexity of the designs, the various power domains, and the use of multiple tools in the design process. Designers can make effective power-performance-area tradeoffs early by using a holistic methodology that includes both architectural and micro-arc... » read more

Achieving Your Low Power Goals With Synopsys Ultra Low Leakage IO


The demand for low power design has intensified with shrinking geometries. At the same time, innovation in battery operated, handheld devices has increased the design complexity by adding more and more functionality. The focus is on power-optimized designs while maintaining low cost and reduced risk. Designers face these complex and contradictory challenges: developing products with the lowest ... » read more

How The Doubling Of Interconnect Bandwidth With PCI Express 6.0 Impacts IP Electrical Validation


As a result of the innovations taking place in CPUs, GPUs, accelerators, and switches, the interface in hyperscale datacenters now requires faster data transfers both between compute and memory and onto the network. PCI Express (PCIe) provides the backbone for these interconnects and is used to build protocols such as Computer Express Link (CXL) and Universal Chiplet Interconnect Express (UCIe... » read more

Accelerating Coverage Closure With AI-Based Verification Space Optimization


Coverage is at the heart of all modern semiconductor verification. There is no maxim more fundamental to this process than “if you haven’t exercised it, you haven’t verified it.” Although covering a particular aspect of a chip design does not guarantee that all bugs are found — bug effect propagation and checker quality are also key factors — it is certainly true that bugs cannot po... » read more

Meeting The Major Challenges Of Modern Memory Design


Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5... » read more

Threat Modeling, Decoded — Charting The Security Journey


Connected systems are part of the modern world. There is virtually no aspect of life that is not available online, from shopping and booking tickets to dating, banking, and attending medical appointments. And these trends show no sign of stopping. On the contrary, many services are moving to digital-first or digital-only models, and every day, new products— from toasters to autonomous vehicle... » read more

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