Tom Anderson

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Tom Anderson is technical marketing consultant working with multiple EDA vendors. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Author's Latest Posts

Three Key Aspects Of IP Quality
By Tom Anderson - 02 Dec, 2021 - Comments: 0

It’s no secret that today’s huge system-on-chip (SoC) projects require massive amounts of design reuse. No team, no matter how talented, can design a billion or more gates from scratch. They use extensive borrowing of RTL code from previous and related projects, plus hundreds of thousands of instantiated IP blocks from internal libraries, open-source repositories, development partners, and ... » read more

GapFree Processor Verification
By Tom Anderson - 26 Mar, 2020 - Comments: 0

Not so long ago, many semiconductor and system suppliers developed their own processors, often with unique features geared toward specific target applications. Although this innovation has continued for specialty processors such as digital signal-processing (DSP) engines and graphics processing units (GPUs), central processing units (CPUs) largely turned into a two-contestant race between x86 a... » read more

Verification Planning And Management With Formal
By Tom Anderson - 30 Jan, 2020 - Comments: 0

Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances were needed to make wider adoption of formal feasible. These included the standardization of assertion languages, enhanced formal engine performance and capacity, better debug capabilities, and pushbu... » read more

Enabling The RISC-V Ecosystem
By Tom Anderson - 27 Jun, 2019 - Comments: 0

Earlier this year, OneSpin’s Sven Beyer discussed the emerging RISC-V processor and some of its verification challenges. He stated that “RISC-V is hot and stands at the beginning of what may be a major shift in the industry.” In the few intervening months, it has become even more apparent that RISC-V is fundamentally changing system-on-chip (SoC) development. Dozens of commercial and open... » read more

Connectivity Checking Is A Perfect Fit For Formal Verification
By Tom Anderson - 31 Jan, 2019 - Comments: 0

Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific verification problems. Further, many of these app... » read more

Integrating Results And Coverage From Simulation And Formal
By Tom Anderson - 25 Oct, 2018 - Comments: 0

Not so long ago, formal verification was considered an exotic technology used only by specialists for specific verification challenges such as cache coherency. As chips have grown ceaselessly in size and complexity, the traditional verification method of simulation could not keep pace. The task of generating and running enough tests consumed enormous resources in terms of engineers, simulation ... » read more

The Skies Over EDA Are Finally Cloudy
By Tom Anderson - 28 Jun, 2018 - Comments: 0

EDA companies have been talking for years about providing access to their tools in the cloud, including more articles than I can count with titles about the EDA forecast being cloudy, clouds on the horizon, and so forth. The title of this post continues the dubious tradition of cloud-based puns, but there’s no future tense involved. Recent announcements from several EDA companies make it appe... » read more

A Combined Design And Verification Flow For Safety-Critical Designs
By Tom Anderson - 24 May, 2018 - Comments: 0

By Tom Anderson and Srikanth Rengarajan I welcome my co-author for today’s post, Srikanth Rengarajan, vice president of product and business development from Austemper Design Systems. We would like to focus on safety-critical designs, a topic very much in the news these days because of the public’s fascination with autonomous vehicles. This consumer category now joins medical electron... » read more

Why Your FPGA Synthesis Flow Requires Verification
By Tom Anderson - 26 Apr, 2018 - Comments: 0

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

Making Sense Of Safety Standards
By Tom Anderson - 22 Feb, 2018 - Comments: 0

If you’re involved in the design or verification of safety-critical electronics, you’ve probably heard about some of the standards that apply to such development projects. If not, then you’re probably puzzled when you read about TÜV SÜD certifying that an EDA tool satisfies functional safety standards ISO 26262 (TCL3/ASIL D), IEC 61508 (T2/SIL 3) and EN 50128 (T2/SIL 3). The industry ha... » read more

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