Author's Latest Posts


Speeding Up AI With Vector Instructions


A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

Using Verification Data More Effectively


Verification is producing so much data from complex designs that engineering teams need to decide what to keep, how long to keep it, and what they can learn from that data for future projects. Files range from hundreds of megabytes to hundreds of gigabytes, depending on the type of verification task, but the real value may not be obvious unless AI/machine learning algorithms are applied to a... » read more

Confusion Grows Over Packaging And Scaling


The push toward both multi-chip packaging and continued scaling of digital logic is creating confusion about how to classify designs, what design tools work best, and how to best improve productivity and meet design objectives. While the goals of design teams remains the same — better performance, lower power, lower cost — the choices often involve tradeoffs between design budgets and ho... » read more

Sensor Fusion Challenges In Cars


The automotive industry is zeroing in on sensor fusion as the best option for dealing with the complexity and reliability needed for increasingly autonomous vehicles, setting the stage for yet another shift in how data from multiple devices is managed and utilized inside a vehicle. The move toward greater autonomy has proved significantly more complicated than anyone expected at first. There... » read more

System-Level Packaging Tradeoffs


Leading-edge applications such as artificial intelligence, machine learning, automotive, and 5G, all require high bandwidth, higher performance, lower power and lower latency. They also need to do this for the same or less money. The solution may be disaggregating the SoC onto multiple die in a package, bringing memory closer to processing elements and delivering faster turnaround time. But ... » read more

New Uses For Assertions


Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Dealing With Device Aging At Advanced Nodes


Premature aging of circuits is becoming troublesome at advanced nodes, where it increasingly is complicated by new market demands, more stress from heat, and tighter tolerances due to increased density and thinner dielectrics. In the past, aging and stress largely were separate challenges. Those lines are starting to blur for a number of reasons. Among them: In automotive, advanced-node... » read more

Formal Verification Becoming Critical To Auto Security, Safety


Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications. Formal has been essential component of automotive semiconductor verification for some time. Even before the advent of ADAS and semi-autonomous vehicles — and functional safety specifications like ISO 26262 and cybersecur... » read more

Challenges In Using AI In Verification


Pressure to use AI/ML techniques in design and verification is growing as the amount of data generated from complex chips continues to explode, but how to begin building those capabilities into tools, flows and methodologies isn't always obvious. For starters, there is debate about whether the data needs to be better understood before those techniques are used, or whether it's best to figure... » read more

Preparing For A Barrage Of Physical Effects


Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

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