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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

When To Expect Domain-Specific AI Chips
By Brian Bailey - 13 Jun, 2024 - Comments: 0

The chip industry is moving toward domain-specific computation, while artificial intelligence (AI) is moving in the opposite direction, creating a gap that could force significant changes in how chips and systems are architected in the future. Behind this split is the amount of time it takes to design hardware and software. In the 18 months since ChatGPT was launched on the world, there has ... » read more

DAC Panel Could Spark Fireworks
By Brian Bailey - 30 May, 2024 - Comments: 1

Panels can often become love fests. While a title may sound controversial, it turns out that everyone quickly finds that all the panelists agree on the major points. This is sometimes the result of how the panel was put together – the proposal came from one company, and they wanted to get their customers or clients onto the panel. They are unlikely to ask a major competitor to be part of the ... » read more

RISC-V Heralds New Era Of Cooperation
By Brian Bailey - 30 May, 2024 - Comments: 0

RISC-V is paving the way for open source to become accepted within the hardware community, creating a level of industry collaboration never seen in the past, while revitalizing the connection between academia and industry. The big question is whether this arrangement is just a placeholder while the industry re-learns how to develop processors, or whether this processor architecture is someth... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

Will Domain-Specific ICs Become Ubiquitous?
By Brian Bailey - 16 May, 2024 - Comments: 0

Questions are surfacing for all types of design, ranging from small microcontrollers to leading-edge chips, over whether domain-specific design will become ubiquitous, or whether it will fall into the historic pattern of customization first, followed by lower-cost, general-purpose components. Custom hardware always has been a double-edged sword. It can provide a competitive edge for chipmake... » read more

Can Models Created With AI Be Trusted?
By Brian Bailey - 06 May, 2024 - Comments: 0

EDA models that are created using AI need to pass more stringent quality and cost benefit analysis compared to many AI applications in the broader industry. Money is hanging on the line if AI gets it wrong, and all the associated costs must be factored into the equation. Models are some of the most expensive things a development team can create, and it is important to understand the value th... » read more

Is There Any Hope For Asynchronous Design?
By Brian Bailey - 25 Apr, 2024 - Comments: 6

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet has never resulted in more than a few experiments. Synchronous design utilizes a clock, where the clock frequency is set by the longest and slowest path in the design. That includes potential var... » read more

Revitalizing DAC
By Brian Bailey - 25 Apr, 2024 - Comments: 0

The 61st Design Automation Conference is just two months away and as I get closer to retirement, I know there will only be a few remaining for me. I entered the EDA industry in 1980, so have been involved with it for almost 45 years. Over that period, I have only missed a few. It is interesting how the conference has changed over the years. In the early days, DAC was only a conference, where... » read more

Memory On Logic: The Good And Bad
By Brian Bailey - 11 Apr, 2024 - Comments: 0

The chip industry is progressing rapidly toward 3D-ICs, but a simpler step has been shown to provide gains equivalent to a whole node advancement — extracting distributed memories and placing them on top of logic. Memory on logic significantly reduces the distance between logic and directly associated memory. This can increase performance by 22% and reduce power by 36%, according to one re... » read more

NoCs In 3D Space
By Brian Bailey - 03 Apr, 2024 - Comments: 0

A network on chip (NoC) has become an essential piece of technology that enables the complexity of chips to keep growing, but when designs go 3D, or when third-party chiplets become pervasive, it's not clear how NoCs will evolve or what the impact will be on chiplet architectures. A NoC enables data to move between heterogeneous computing elements, while at the same time minimizing the resou... » read more

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