Author's Latest Posts

Device Validation: The Ultimate Test Frontier

This article is a condensed version of an article that appeared in the November/December 2022 issue of Chip Scale Review. Adapted with permission. Read the original article at, p. 26. In the early days of space exploration, spacecraft were manned by small teams of astronauts, most of whom were experienced test pilots who ... » read more

HSIO Loopback Turns Challenges Into Opportunities For Test At 112 Gbps

By Dave Armstrong and Don Thompson For both PCIe and Ethernet (IEEE 802.3,) signals are getting mighty small. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are shrinking. Consequently, test requirements for high-speed I/O (HSIO) test are becoming daunting. HSIO test involves measurement of Tx eye height and width, co... » read more

SLT Enables Test Content To Shift Right

By Dave Armstrong, Davette Berry, and Craig Snyder Increasing device complexity and the continuing drive for higher levels of quality are fostering a reconsideration of test strategies. To be effective, test engineers must choose how to optimally deploy test content, from wafer probing to system-level test (SLT). A March 2019 TestConX presentation1 outlines how test content is typically allo... » read more