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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Monolithic Vs. Heterogeneous Integration
By Ed Sperling - 24 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

Unbundling Analog From Digital Where It Makes Sense
By Ed Sperling - 17 Oct, 2024 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing in analog design with the shift toward heterogeneous integration and more safety- and mission-critical applications with Mo Faisal, president and CEO of Movellus; Hany Elhak, executive director of product management at Synopsys; Cedric Pujol, product manager at Keysight; and Pradeep Thiagarajan, principal product manager for custom I... » read more

Big Changes In Optical Inspection
By Ed Sperling - 16 Oct, 2024 - Comments: 0

Optical inspection always has been the workhorse technology for finding defects in chips. It's fast, cost-efficient, and generally reliable enough for most chips. But as logic scales into the angstrom range, and as systems become collections of chiplets, optical inspection needs to be combined with other types of inspection such as X-ray and acoustic. Kyle Vander Schaaf, application engineer at... » read more

New Challenges In IC Reliability
By Ed Sperling - 15 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips, how it is changing, and where the new challenges are, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech soluti... » read more

EDA And IP Revenue Grow, But Markets Are Shifting
By Ed Sperling - 07 Oct, 2024 - Comments: 0

EDA and IP revenue grew 18.2% worldwide to $4.69 billion in Q2, year-over-year, with all product categories and regions reporting increases, but a drill down into the numbers shows some new pockets of growth and weakness The Asia/Pacific region exhibited strong growth once again, but the dynamics in that market have changed significantly. China is no longer the primary revenue generator for ... » read more

Working With Chiplets
By Ed Sperling - 02 Oct, 2024 - Comments: 0

The usual method of migrating to the next process node to cram more features onto a piece of silicon no longer works. It's too expensive, and too limited for most applications. The path forward is now heterogeneous chiplets targeted at specific markets, and while logic will continue to scale, other features are being separated out into chiplets developed using different process technologies. Th... » read more

Data Routing In Heterogeneous Chip Designs
By Ed Sperling - 30 Sep, 2024 - Comments: 0

Ensuring data gets to where it's supposed to go at exactly the right time is a growing challenge for design engineers and architects developing heterogeneous systems. There is more data moving around these chips with dozens of targets, which makes routing signals much more complicated. Ronen Perets, senior product marketing manager at Cadence Design Systems, talks about some of the new problems... » read more

Emerging Technologies Driving Heterogeneous Integration
By Ed Sperling - 24 Sep, 2024 - Comments: 0

As chips are disaggregated into chiplets, more features are being added into these devices that chipmakers were unable to include in the past due to reticle size limits and the high cost of scaling everything to the latest process node. This has opened the door to new architectures, new materials such as glass substrates, and a variety of new challenges. Dick Otte, president and CEO of Promex I... » read more

Striking A Balance On Efficiency, Performance, And Cost
By Ed Sperling - 11 Sep, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power-related issues such as voltage droop, application-specific processing elements, the impact of physical effects in advanced packaging, and the benefits of backside power delivery, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product m... » read more

New AI Processors Architectures Balance Speed With Efficiency
By Ed Sperling - 04 Sep, 2024 - Comments: 1

Leading AI systems designs are migrating away from building the fastest AI processor possible, adopting a more balanced approach that involves highly specialized, heterogeneous compute elements, faster data movement, and significantly lower power. Part of this shift revolves around the adoption of chiplets in 2.5D/3.5D packages, which enable greater customization for different workloads and ... » read more

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