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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Preparing For 3D-ICs
By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Unknowns Driving Up The Cost Of Auto IC Reliability
By Ed Sperling - 08 Feb, 2022 - Comments: 2

Automotive chipmakers are considering a variety of options to improve the reliability of ICs used for everything from sensors to artificial intelligence. But collectively they could boost the number of process steps, increase the time spent in manufacturing and packaging, and stir up concerns about the amount of data that needs to be collected, shared, and stored. Accounting for advanced pro... » read more

More Manufacturing Issues, More Testing
By Ed Sperling - 08 Feb, 2022 - Comments: 0

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

Design Technology Co-Optimization
By Ed Sperling - 18 Jan, 2022 - Comments: 0

Rising complexity is making it increasingly difficult to optimize chips for yield and reliability. David Fried, vice president of computational products at Lam Research, examines the benefits of automated rules to manage the relationship between layout and design requirements on one side, and process flows and rules/checks on the other. Benefits include reduced margin, shortened time to market,... » read more

The Risk Of Losing Track Of Your IP
By Ed Sperling - 12 Jan, 2022 - Comments: 0

What happens when you misuse IP, intentionally or otherwise? Pedro Pires, applications engineer at Cliosoft, talks about the challenges of keeping track of IP across multiple chip design projects, which can grow to include dozens of third-party IP blocks, last for long periods of years, and span multiple continents. » read more

Setting Ground Rules For 3D-IC Designs
By Ed Sperling - 12 Jan, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

The Importance Of Layering Data
By Ed Sperling - 11 Jan, 2022 - Comments: 0

The chip industry generates enormous quantities of data, from design through manufacturing, but much of it is unavailable or incomplete. And even when and where it is available, it is frequently under-utilized. While there has been much work done in terms of establishing traceability and data formats, the cross-pollination of data between companies and between equipment makers at various pro... » read more

The Gargantuan 5G Chip Challenge
By Ed Sperling - 11 Jan, 2022 - Comments: 0

Blazing fast upload and download speeds for cellular data are coming, but making the technology function as expected throughout its expected lifetime is an enormous challenge that will require substantial changes across the entire chip ecosystem. While sub-6GHz is an evolutionary step from 4G LTE, the real promise of 5G kicks in with millimeter-wave (mmWave) technology. But these higher-freq... » read more

Always-On DSPs
By Ed Sperling - 28 Dec, 2021 - Comments: 0

There are tradeoffs between powering circuits down to save power and waking them up to respond to voice and visual commands. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the best ways to deploy digital signal processors, why multiple DSPs are often better than just one, and what penalties there are for various approaches. » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

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