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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

Radiation Hardening Chips For Outer Space
By Ed Sperling - 14 Dec, 2021 - Comments: 0

What’s the difference between radiation tolerant and radiation hardening, and where is each one used? Minal Sawant, director of the aerospace and defense vertical market at Xilinx, talks about different striations in the Earth’s atmosphere, how those various levels can affect radiation, and what impact that has on the functionality of increasingly dense chip circuits over extended periods o... » read more

Why It’s So Difficult — And Costly — To Secure Chips
By Ed Sperling - 02 Dec, 2021 - Comments: 0

Rising concerns about the security of chips used in everything from cars to data centers are driving up the cost and complexity of electronic systems in a variety of ways, some obvious and others less so. Until very recently, semiconductor security was viewed more as a theoretical threat than a real one. Governments certainly worried about adversaries taking control of secure systems through... » read more

Creating IoT Devices That Will Remain Secure
By Ed Sperling - 30 Nov, 2021 - Comments: 0

What’s secure today may not be secure in the future, and even if you include an IoT device with state-of-the-art security, it may be surrounded by less secure devices. Steve Hanna, distinguished engineer at Infineon, examines the impact of security on IoT adoption, why resilience across a system is the new target for secure designs, and how to minimize the impact of less secure devices. » read more

End-To-End Traceability
By Ed Sperling - 29 Nov, 2021 - Comments: 0

Despite standards such as ISO 26262 and IEC 61508, there are still disconnects and gaps in the supply chain and design-through-manufacturing flows. Kurt Shuler, vice president of marketing at Arteris IP, digs into what's missing, why changes made in one area are not reflected in other areas and throughout the product lifecycle, and why various different phases of the flow don't always match up ... » read more

1.6 Tb/s Ethernet Challenges
By Ed Sperling - 16 Nov, 2021 - Comments: 0

Moving data at blazing fast speeds sounds good in theory, but it raises a number of design challenges. John Swanson, senior product marketing manager for high-performance computing digital IP at Synopsys, talks about the impact of next-generation Ethernet on switches, the types of data that need to be considered, the causes of data growth, and the size and structure of data centers, both in the... » read more

Reviving The IPO Route For IP Companies
By Ed Sperling - 01 Nov, 2021 - Comments: 0

K. Charles Janac, chairman and CEO of Arteris IP, sat down with Semiconductor Engineering to talk about the company's recent decision to go public, including the benefits and risks of operating as a public IP company. SE: The rule of thumb used to be $20 million in revenue was needed for an IP company to do an IPO at the turn of the Millennium, and then it increased to $40 million about a de... » read more

What’s Missing For Designing Chips At The System Level
By Ed Sperling - 01 Nov, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Week In Review: Auto, Security, Pervasive Computing
By Ed Sperling - 22 Oct, 2021 - Comments: 0

An investigation by the Automobile Association of America found that lane-keeping assist and automatic emergency braking, both high-profile ADAS features, are prone to failure in rain. According to the report, 69% of tests conducted with simulated rainfall resulted in test vehicles crossing lane markers, and 33% of simulations resulted in collisions at 35 mph. Surprisingly, risk of accidents di... » read more

Total Critical Area For Optimizing Test Patterns
By Ed Sperling - 19 Oct, 2021 - Comments: 0

Increasing complexity at advanced nodes makes it much harder to locate defects and latent defects because there is more surface area to cover and much less space between the various components in a leading-edge chip design. Ron Press, technology enablement director at Siemens Digital Industries Software, talks about why it’s so important to predict where defects are most likely to occur in th... » read more

The Everything New Syndrome
By Ed Sperling - 12 Oct, 2021 - Comments: 0

Technology is all about the latest features, the fastest processing, with the lowest power. While that sounds great in marketing pitch, any or all of those factors don't necessarily equate to a better product or long-term user satisfaction. There's a reason semiconductor companies are conservative by nature. They want to know that when they spend tens or hundreds of millions of dollars on a ... » read more

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