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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

DAC 2020: Virtual And Different
By Ed Sperling - 08 Jun, 2020 - Comments: 0

Zhuo Li, group director at Cadence, and Harry Foster, chief scientist at Mentor, a Siemens Business, talk about the changes in content for this year's Design Automation Conference. » read more

Designing The Next Big Things
By Ed Sperling - 05 Jun, 2020 - Comments: 0

The edge is a humongous opportunity for the semiconductor industry. The problem, despite its name, is that it's not a single thing. It will be comprised of thousands of different chips and systems, and very few will be sold in large volumes. The edge is the culmination of decades of improvement in power and performance, coupled with the architectural creativity that has exploded since the bene... » read more

Conflicting Demands At The Edge
By Ed Sperling - 04 Jun, 2020 - Comments: 0

Semiconductor Engineering sat down to define what the edge will look like with Jeff DeAngelis, managing director of the Industrial and Healthcare Business Unit at Maxim Integrated; Norman Chang, chief technologist at Ansys; Andrew Grant, senior director of artificial intelligence at Imagination Technologies; Thomas Ensergueix, senior director of the automotive and IoT line of business at Arm; V... » read more

High-Speed SerDes At 7/5nm
By Ed Sperling - 02 Jun, 2020 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how to optimize PHYs for integration on all four corners of an SoC, as well as the PPA implications of moving large amounts of data across and around a chip. » read more

An Eye For An AI
By Ed Sperling - 01 Jun, 2020 - Comments: 0

AI comes in multiple forms and flavors. The challenge is choosing the right one for the right purpose, and recognizing that just because AI can be applied to a particular process or problem doesn't mean it should be. While AI has been billed as a ideal solution for just about every problem, there are three primary requirements for a successful application. First, there needs to be sufficient q... » read more

What Will The Next-Gen Verification Flow Look Like?
By Ed Sperling - 28 May, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; and Nasr Ullah, senior director of performance architecture at SiFive. What follows are exc... » read more

Ensuring HBM Reliability
By Ed Sperling - 27 May, 2020 - Comments: 0

Igor Elkanovich, CTO of GUC, and Evelyn Landman, CTO of proteanTecs, talk with Semiconductor Engineering about difficulties that crop up in advanced packaging, what’s redundant and what is not when using high-bandwidth memory, and how continuous in-circuit monitoring can identify potential problems before they happen. » read more

The Chemistry Of Semiconductors
By Ed Sperling - 21 May, 2020 - Comments: 0

At each new process node, the chemistry of chip manufacturing has become much more complex than at previous nodes. But at 5nm and below, it's going to get orders of magnitude more complex. For the first few decades, the chemistry of chips was largely shielded from view for most of the industry. Caustic gases were relatively well understood because they are a potential health hazard, but the ... » read more

Cleaning Data For Final Test
By Ed Sperling - 20 May, 2020 - Comments: 0

John O’Donnell, CEO of yieldHUB, talks about why data integrity is so critical for final test, what can cause it to be less-than-perfect, what’s needed to improve the quality of that data, and how that impacts the overall yield in a fab. » read more

Rising Packaging Complexity
By Ed Sperling - 19 May, 2020 - Comments: 1

Synopsys’ Rita Horner looks at the design side of advanced packaging, including how tools are chosen today, what considerations are needed for integrating IP while maintaining low latency and low power, why this is more complex in some ways than even the most advanced planar chip designs, and what’s still missing from the tool flow. » read more

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