Geoff Tate

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Geoff Tate is a technology strategy advisor. He was the founding CEO of Flex Logix (now part of Analog Devices). Before that, he was the founding CEO of Rambus, and prior to that he was senior vice president of AMD's processor group. He received his BSc in computer science from the University of Alberta, and an MBA from Harvard Business School.

Author's Latest Posts

The Next Generation Of Embedded FPGA
By Geoff Tate - 03 Aug, 2023 - Comments: 0

EFLX eFPGA has been in use in SoCs for more than 5 years, hardware and software. More than 40 chips have been licensed to use EFLX eFPGA and more than 20 chips are working in silicon. Big customers like Renesas are planning high volumes and families of chips using eFPGA. As we have worked with customers our architecture has evolved from EFLX Gen 1.0 to Gen 2.0, 2.1, 2.2, 2.3 and now in 2023 ... » read more

Connect To Any Chip With Programmable GPIO
By Geoff Tate - 06 Apr, 2023 - Comments: 0

Your MCU/SoC today may have several options for GPIO connections: UART, SPI, I2C. But there are dozens of variations and kinds of GPIO interface protocols: you don’t have enough pins to provide all of them as hardwired options. As a result, a significant number of your customers either can’t use your chip because they need to connect to another with a GPIO interface you don’t support, ... » read more

The Importance Of Metal Stack Compatibility For Semi IP
By Geoff Tate - 02 Mar, 2023 - Comments: 0

Every foundry and every node is different, but for every foundry/node there are multiple supported metal stacks. Some chips use a lot more metal layers than others. A common rule of thumb is each metal layer increases wafer cost 10%. So, a chip with 5 more metal layers than another will cost 50%+ more. The most complex, high performance chips, including performance FPGAs, typically use AL... » read more

Micro FPGAs And Embedded FPGAs
By Geoff Tate - 02 Feb, 2023 - Comments: 0

When people hear “FPGA” they think “big, expensive, power hungry.”  But it doesn’t need to be that way. Renesas has announced their Forge FPGA family. Details are at their website and in one of the many articles that covered their press release. Forge FPGAs show that FPGAs don’t have to be big, power hungry, and expensive. Forge FPGAs are tiny, draw standby current measure... » read more

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility
By Geoff Tate - 05 Jan, 2023 - Comments: 0

Systems companies like FPGA because it gives parallel processing performance that can outdo processors for many workloads and because it can be reconfigured when standards, algorithms, protocols or customer requirements change. But FPGAs are big, burn a lot of power and are expensive. Customers would like to integrate them into their adjacent SoC if possible. Dozens of customers are now u... » read more

Edge Inference Applications And Market Segmentation
By Geoff Tate - 03 Dec, 2020 - Comments: 0

Until recently, most AI was in data centers/cloud and most of that was training. Things are changing quickly. Projections are AI sales will grow rapidly to tens of billions of dollars by the mid 2020s, with most of the growth in edge AI inference. Data center/cloud vs. edge inference: What’s the difference? The data center/cloud is where inference started on Xeons. To gain efficiency, much ... » read more

ResNet-50 Does Not Predict Inference Throughput For MegaPixel Neural Network Models
By Geoff Tate - 05 Nov, 2020 - Comments: 1

Customers are considering applications for AI inference and want to evaluate multiple inference accelerators. As we discussed last month, TOPS do NOT correlate with inference throughput and you should use real neural network models to benchmark accelerators. So is ResNet-50 a good benchmark for evaluating relative performance of inference accelerators? If your application is going to p... » read more

One More Time: TOPS Do Not Predict Inference Throughput
By Geoff Tate - 08 Oct, 2020 - Comments: 0

Many times you’ll hear vendors talking about how many TOPS their chip has and imply that more TOPS means better inference performance. If you use TOPS to pick your AI inference chip, you will likely not be happy with what you get. Recently, Vivienne Sze, a professor at MIT, gave an excellent talk entitled “How to Evaluate Efficient Deep Neural Network Approaches.” Slides are also av... » read more

Apples, Oranges & The Optimal AI Inference Accelerator
By Geoff Tate - 03 Sep, 2020 - Comments: 0

There are a wide range of AI inference accelerators available and a wide range of applications for them. No AI inference accelerator will be optimal for every application. For example, a data center class accelerator almost certainly will be too big, burn too much power, and cost too much for most edge applications. And an accelerator optimal for key word recognition won’t have the capabil... » read more

Integrating FPGA: Comparison Of Chiplets Vs. eFPGA
By Geoff Tate - 15 Jul, 2020 - Comments: 0

FPGA is widely popular in systems for its flexibility and adaptability. Increasingly, it is being used in high volume applications. As volumes grow, system designers can consider integration of the FPGA into an SoC to reduce cost, reduce power and/or improve performance. There are two options for integrating FPGA into an SoC: FPGA chiplets, which replace the power hungry SERDES/PHYs wit... » read more

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